Philip Brisk

Cette personne n’est plus à l’EPFL

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Publications associées (34)

Compressor Tree Synthesis on Commercial High-Performance FPGAs

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and ...

2011

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; ho ...

2010

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Fast, Nearly Optimal ISE Identification with I/O Serialization through Maximal Clique Enumeration

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with instruction set extensions (ISEs) that exec ...

2010

MPSoC Design using Application-Specific Architecturally Visible Communication

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide high-throughput communication for streaming applications. Producer/consumer relationships map poorly onto cache-based MPSo ...

Springer-Verlag2009

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

The interference graph for a procedure in Static Single Assignment (SSA) Form is chordal. Since the k-colorability problem can be solved in polynomial-time for chordal graphs, this result has generated interest in SSA-based heuristics for spilling and coal ...

Springer US2009

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

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