Publications de Nithin George | EPFL Graph Search

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs offer high performance coupled with energy efficiency making them extremely attractive computational resources within a cloud ecosystem. However, to achieve this integration and make them easy to program, we first need to enable users with varying ex ...

2017

Design Space Exploration of LDPC Decoders Using High-Level Synthesis

Paolo Ienne, Nithin George, David Novo Bruna, Vitor Silva, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2017

Designing a Virtual Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Ieee2016

Enriching C-based High-Level Synthesis with parallel pattern templates

Paolo Ienne, Lana Josipovic, Nithin George

2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Automatic support for multi-module parallelism from computational patterns

Paolo Ienne, David Novo Bruna, Nithin George, David Loyd Andrews

2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Paolo Ienne, David Novo Bruna, Vitor Silva, Nithin George, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2015