David Novo Bruna

Cette personne n’est plus à l’EPFL

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Publications associées (16)

Improved carry chain mapping for the VTR flow

Paolo Ienne, Grace Zgheib, David Novo Bruna, Ana Petkovska

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Paolo Ienne, Mirjana Stojilovic, Philip Brisk, David Novo Bruna

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing ne ...

Institute of Electrical and Electronics Engineers2013

Cracking The Complexity Of Fixed-Point Refinement In Complex Wireless Systems

Paolo Ienne, David Novo Bruna

Fixed-point arithmetic leads to efficient implementations. However, the optimization process required to size each of the implementation signals can be prohibitively complex. In this paper, we introduce a new divide-and-conquer method that is able to appro ...

Ieee2013

Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime

Paolo Ienne, Xavier Jimenez, David Novo Bruna

Hybrid flash architectures combine static partitions in Sing le Level Cell (SLC) mode with partitions in Multi Level Cell (MLC) mode. Compared to MLC-only solutions, the former exploits fast and short random writes while the latter brings large capacity. O ...

Ieee2012

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Gabriel Falcao Paiva Fernandes, Madhura Purnaprajna

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

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