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Lukas Kull

Cette personne n’est plus à l’EPFL

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Publications associées (21)

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-t ...

Institute of Electrical and Electronics Engineers2017

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work describes a NRZ receiver data-path fabricated in 14nm bulk FinFET technology and characterized in an 850nm VCSEL based optical link up to 64Gb/s. It achieves 1.42pJ/bit energy efficiency while recovering PRBS-7 data (BER< 10-12) modulated by a VC ...

Ieee2017

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Volkan Cevher, Yusuf Leblebici, Cosimo Aprile, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channe ...

2015

High-Speed CMOS ADC Design for 100Gb/s Communication Systems

Lukas Kull

EPFL2014

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a ...

2014

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS tra ...

2014

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...

2013

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alt ...

Institute of Electrical and Electronics Engineers2013

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A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

Volkan Cevher, Yusuf Leblebici, Cosimo Aprile, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

2015

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

2014

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

Institute of Electrical and Electronics Engineers2013

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

2013