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Thomas Ropars

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Publications associées (10)

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On the Performance of Delegation over Cache-Coherent Shared Memory

André Schiper, Thomas Ropars, Darko Petrovic

Delegation is a thread synchronization technique where access to shared data is performed through a dedicated server thread. When a client thread requires shared data access, it makes a request to a server and waits for a response. This paper studies deleg ...

2015

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As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ult ...

2014

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Assoc Computing Machinery2014

High-Throughput Maps on Message-Passing Manycore Architectures: Partitioning versus Replication

André Schiper, Thomas Ropars, Omid Shahmirzadi

The advent of manycore architectures raises new scalability challenges for concurrent applications. Implementing scalable data structures is one of them. Several manycore architectures provide hardware message passing as a means to efficiently exchange dat ...

2014

High-Throughput Maps on Message-Passing Manycore Architectures: Partitioning versus Replication

André Schiper, Thomas Ropars, Omid Shahmirzadi

2014

Replication for Send-Deterministic MPI HPC Applications

André Schiper, Thomas Ropars, Arnaud Lefray

Replication has recently gained attention in the context of fault tolerance for large scale MPI HPC applications. Existing implementations try to cover all MPI codes and to be independent from the underlying library. In this paper, we evaluate the advantag ...

2013

SPBC: Leveraging the Characteristics of MPI HPC Applications for Scalable Checkpointing

André Schiper, Thomas Ropars

The high failure rate expected for future supercomputers requires the design of new fault tolerant solutions. Most checkpointing protocols are designed to work with any message-passing application but suffer from scalability issues at extreme scale. We tak ...

2013

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Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel ...

2012

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This paper focuses on the design of an asynchronous broadcast primitive on the Intel SCC. Our solution is based on OC-Bcast, a state-of-the-art k-ary tree synchronous broadcast algorithm that leverages the parallelism provided by on-chip Remote Memory Acce ...

2012

High performance computing will probably reach exascale in this decade. At this scale, mean time between failures is expected to be a few hours. Existing fault tolerant protocols for message passing applications will not be efficient anymore since they eit ...

2012