Personne
Giovanni Ansaloni
Publications associées (49)
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding
David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, William Andrew Simon
Edge devices must support computationally demanding algorithms, such as neural networks, within tight area/energy budgets. While approximate computing may alleviate these constraints, limiting induced errors remains an open challenge. In this paper, we pro ...
2021Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence
David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse
This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation ...
2021i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing
David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Soumya Subhra Basu, Loris Gérard Duch
Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, than ...
2019Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors
David Atienza Alonso, Giovanni Ansaloni, Amir Aminifar, Leila Cammoun
Event detection and classification algorithms are resilient towards aggressive resource-aware optimisations. In this paper, we leverage this characteristic in the context of smart health monitoring systems. In more detail, we study the attainable benefits ...
IEEE2019Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications
David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Soumya Subhra Basu, Loris Gérard Duch
In the Internet-of-Things (IoT) era, there is an increasing trend to enable intelligent behavior in edge computing sensors. Thus, a new generation of smart wearable devices for health monitoring is being developed, able to perform complex Digital Signal Pr ...
IEEE2018A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing
David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Luca Benini
In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiog ...
Institute of Electrical and Electronics Engineers2017HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis
David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch
Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by ...
Ieee-Inst Electrical Electronics Engineers Inc2017An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery
David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is oe ...
2017An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery
David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch
The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is ofte ...
Assoc Computing Machinery2017A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis
David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch
This paper introduces a novel computing architecture devoted to the ultra-low power analysis of multiple bio-signals. Its structure comprises several processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable ...
2016