The aim of this thesis is to implement, analyze and improve the selected low noise clock
generation and distribution techniques for ADC implementations. The thesis is divided into
two parts. The first part focuses on the sampling phase generation and distr ...
The analysis of the effect of sub-sampling phase detector (SSPD) timing nonidealities on Type-I sub-sampling phase-locked loop (SSPLL) is presented. The nonidealities considered are the delay between the complementary sampling clocks and the propagation de ...
The discrete time analysis of the phase detector linear range extension in the first and the second order sub sampling phase-locked loop (SSPLL) is presented. The aim is to understand how much the stability and the pull-in range are affected by the linear ...
In this paper we present the design of a pro- grammable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide- by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and ...
