Andrea Ruffino

Biographie

Andrea Ruffino received the B.Sc. degree (cum laude) in Engineering Physics from Politecnico di Torino, Turin, Italy, in 2013, the triple joint M.Sc. degree (cum laude) in Micro and Nanotechnologies for Integrated Systems from Politecnico di Torino, Institut National Polytechnique de Grenoble (INPG), Grenoble, France, and École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland, in 2015 and the Ph.D. degree in Microsystems and Microelectronics from EPFL in 2021. From 2015 to 2016, he was with Hypres, Inc., Elmsford, NY, USA, working on the design of superconducting readout circuits in rapid single flux quantum (RSFQ) technology for superconducting nanowire single-photon detectors. In 2016, he joined EPFL as a Research Assistant and from 2017 to 2018 he was a Visiting Research Assistant at Delft University of Technology, Delft, The Netherlands. Since 2016 he has been with EPFL, where he is working on cryogenic CMOS electronics for qubit readout and control, focusing on single-chip cryo-CMOS transceivers for scalable silicon quantum computers. His main research interests include analog and RF integrated circuit design, cryogenic CMOS electronics for quantum computing applications, superconducting electronics and sensors. Dr. Ruffino was also among the Best Student Paper Award finalists at the IEEE Radio-Frequency Integrated Circuits (RFIC) Symposium 2019 and he is a recipient of the IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award for 2020-2021.

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A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits

Edoardo Charbon, Yatao Peng, Andrea Ruffino

In this article, a cryo-CMOS receiver integrated with a frequency synthesizer for scalable multiplexed readout of qubits is presented, focusing on radio frequency (RF) reflectometry readout of silicon-based semiconductor spin qubits/quantum dots. The proposed spin qubit readout chip consists of a wideband low noise amplifier (LNA), a quadrature mixer, a complex filter, a pair of in-phase/quadrature (I/Q) intermediate frequency (IF) amplifier chains, and a type-II charge-pump phase-locked loop (PLL) with a programmable frequency divider providing local oscillator (LO) signals. Noise optimizations are applied to the LNA design and the quadrature active mixer design to obtain the required performance. A mode-switching complementary voltage-controlled oscillator (VCO) is proposed to achieve low-power and low-phase noise in a wide-frequency tuning range (46.5%). Circuit modifications and design considerations for robust cryogenic temperature operation are presented and discussed. Measurements show that the receiver provides an average gain of 65 dB, a minimum noise figure of 0.5 dB, an IF bandwidth of 0.1-1.5 GHz, and an image rejection ratio of 23 dB at 3.5 K with a power consumption of 108 mW. This cryo-CMOS receiver with frequency synthesizer for spin qubit readout is a first step toward fully-integrated qubit readout and control.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

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A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Edoardo Charbon, Yatao Peng, Andrea Ruffino

An integrated circuit fabricated using industry-standard 40 nm complementary metal-oxide-semiconductor technology can combine silicon quantum devices, digital addressing and analogue multiplexed dispersive readout electronics. As quantum computers grow in complexity, the technology will have to evolve from large distributed systems to compact integrated solutions. Spin qubits in silicon quantum dots are thought to offer good scalability because both spin-carrying quantum dots and support complementary metal-oxide-semiconductor (CMOS) electronics can, in principle, be monolithically integrated on a single chip. However, monolithically integrated quantum-classical hybrid circuits based on industry-standard CMOS technology remain limited. Here we report a millikelvin integrated circuit fabricated using 40 nm CMOS technology that integrates silicon quantum-dot arrays with support electronics in an architecture that allows the array to be efficiently addressed and read. The architecture contains integrated microwave lumped-element resonators for dispersive sensing of the charge state of the quantum dots, mediated via digital transistors in a column-row-addressing distribution. With the chip, we demonstrate combined time- and frequency-division multiplexing, which scales sublinearly the resources as well as footprint required for readout.

NATURE PORTFOLIO2021

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A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported. The LNA specifications are derived from the readout of semiconductor quantum bits at 4.2 K, whose quantum information signals are characterized as phase-modulated signals. To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of the input transistor is exploited. The goal is to involve a resistive and capacitive load into the input impedance match of a common-source stage with source inductive degeneration. The capacitive load is created by an LC parallel tank whose resonant frequency is lower than the operating frequency. The achieved non-constant in-band equivalent capacitance is proven to be beneficial to input impedance matching. The resistive part of the load is provided by the transconductance of the cascode stage implicitly. An inductor is added to the gate of the cascode transistor to suppress its noise, and a transformer-based resonator with two resonant frequencies serves as the load of the first stage, thus extending the operating bandwidth. Design considerations for the cryogenic temperature operation of the LNA are proposed and analyzed. The LNA achieves a measured gain (S₂₁) of 35 ± 0.5 dB, return loss > 12 dB, and NF of 0.75-1.3 dB across the band (4.1-7.9 GHz), with 51.1-mW power consumption at room temperature, while it shows a measured gain of 42 ± 3.3 dB, and NF of 0.23-0.65 dB with 39-mW power consumption at 4.2 K between 4.6 and 8 GHz. To the best of our knowledge, this is the first report of a cryogenic LNA based on a bulk CMOS process working above 4 GHz showing sub-1-dB NF both at room and cryogenic temperatures.

2021

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