Andrei Ardelean | EPFL Graph Search

Andrei Ardelean received the B.Sc. degree in Electronics from "Politehnica" University of Timisoara, Timisoara, Romania, in 2015, and the M.Sc. degree in Microelectronics from the Delft University of Technology, Delft, Netherlands, in 2017. He is currently working towards his Ph.D. in the AQUA Laboratory at EPFL. His main research interests are single-photon counting time-correlated image sensors for real time phasor-based fluorescence lifetime imaging microscopy.

Computational Imaging SPAD Cameras

Andrei Ardelean

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the raw pixel data and reduce the amount of information that needs to be read from the sensor. With the emergence of large format single-photon avalanche diode (SPAD) imagers, the need for on-chip processing has become more evident, as the output data rate of such detectors is pushing the limit of even modern interfaces.The aim of the thesis is to develop sensor architectures for computational imaging that overcome limitations of conventional SPAD imagers and can operate at high frame rates with manageable output data rates. Three sensors are designed in different technology nodes, from 180nm 2D to 3D-stacked 45/22nm and 180/16nm, backside and front-side illuminated.A novel token-based readout technique is developed to improve system frame rate by reducing the readout time through omission of dark pixels. The technique is implemented in kiloPhase, a 32x32 gated SPAD imager with vector processing capabilities that can achieve 4.38ns gates and can operate at 227fps in 10bit intensity mode, a 12% increase compared to conventional readout. An improved, massively parallel version of the architecture is implemented in MegaPhase, a 1-megapixel SPAD imager consisting of 16384 processing cores that can perform addition and multiplication operations on the raw pixel data. The SPADs can be binned with multiple granularities to increase the pixel dynamic range and reduce the required exposure time. Simulations show a frame rate increase of up to 170x when operating as an intensity imager and 56x in gated fluorescence lifetime imaging (FLIM) mode.Finally, UltraPhase, the first fully reconfigurable SPAD processing architecture is developed and consists of 18 independent processors running at 140MOPS with a power consumption of less than 94.6GOPS/W. Each processor can execute up to 256 instructions per program and contains a reconfigurable front end that can implement a wide range of combinatorial functions and a timing module that can be configured to measure photon arrival timestamps.

EPFL2023

Massively parallel, real-time multispeckle diffuse correlation spectroscopy using a 500 × 500 SPAD camera

Andrei Ardelean, Claudio Bruschini, Edoardo Charbon, Francesco Marsili, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

Diffuse correlation spectroscopy (DCS) is a promising noninvasive technique for monitoring cerebral blood flow and measuring cortex functional activation tasks. Taking multiple parallel measurements has been shown to increase sensitivity, but is not easily scalable with discrete optical detectors. Here we show that with a large 500 × 500 SPAD array and an advanced FPGA design, we achieve an SNR gain of almost 500 over single-pixel mDCS performance. The system can also be reconfigured to sacrifice SNR to decrease correlation bin width, with 400 ns resolution being demonstrated over 8000 pixels.

2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Andrei Ardelean, Claudio Bruschini, Edoardo Charbon, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gates, guaranteed by the circuit architecture to be nonoverlapping and covering the totality of the sensor's exposure period. The gates can be adjusted with a temporal resolution of 17.9 ps, and the minimum measured gate width is 0.99 ns; to our knowledge, the shortest reported to date among large-format SPAD imagers. In the dual-channel mode, the burst frame rate is 49.8 and 97.7 kframes/s in the single-channel mode. A 2690-MB/s PCI express (PCIe) interface has been added to the data acquisition framework, enabling continuous operation at approximately 44 and 88 kframes/s. Due to optimizations of the gate-signal tree, we achieved a significant reduction to gate skew and gate width variation, which is negligible with respect to the SPAD temporal jitter. These improvements, along with sub-10-cps dark count rate (DCR) per pixel and 50% maximum photon detection probability (PDP), result in a sensor particularly well suited for fast acquisition fluorescence lifetime imaging microscopy (FLIM) experiments, for which we demonstrate reduced dispersion versus a single-gated sensor.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Computational Imaging SPAD Cameras

Andrei Ardelean

EPFL2023