Fulvio Martinelli
In the last years, sub-nanosecond time-resolved particle detectors have been object of research by many companies and institutes since they represent an efficient tool to improve the performance of detecting systems for various applications such as High Energy Physics (HEP) and medical imaging. The work summarized in this thesis focuses on the design, implementation and testing of high-performance electronics in SiGe BiCMOS technology for the development of timing systems such as gamma-photons detectors for PET scanners or Long-Lived Particles (LLPs) detectors for HEP applications. Design solutions and architectures are presented and analysed and their impact on the performance of timing detectors are emphasized. The main contributions of the thesis also include the development of a non-linearity model for the analysis of the impact of mismatches in free-running ring-oscillator based Time-to-Digital Converters (TDCs) and the implementation of various Genetic Algorithms (GAs) for circuit tuning. A comparison of different types of GAs is presented and the impact of their properties on the performance of the circuits to optimize is analysed. This work describes the design solutions adopted for the implementation of two pre-production ASICs for the upgrade of detecting system of the FASER experiment at CERN. One of them was produced to perform an extensive study on different level of integration of the front-end system inside the pixel area. The second represents a smaller version of the final full-reticle ASIC for the FASER experiment. This work reports and highlights the main design challenges related to the implementation of a monolithic 23.2x15.3 mm2 detector. Part of the thesis is focused on the TT-PET project. The latter aims to develop a monolithic pixel detector characterized by a ~30 ps time resolution to be integrated in a small-animal PET scanner. The design of a compact TDC for the TT-PET project is presented. Its architecture is based on a multi-path free-running Ring-Oscillator (RO) featuring a PLL-less event-by-event calibration system. This system is characterized by a ~33 ps Least Significant Bit (LSB) and its compact area, simplicity and power consumption makes this solution particularly suitable for systems in which the integration of many converters is required. Moreover, the aforementioned non-linearity model allowed demonstrating the source of the performance superiority (in terms of linearity) of the presented design. The PLL-less synchronization system was also integrated in the
EPFL2022
