Publications de Joshua Alexander Harrison Klein

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Joshua Alexander Harrison Klein

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to ...

2023

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

2022

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Irem Boybat Kara, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Abu Sebastian

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

2022

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Joshua Alexander Harrison Klein

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Graph Chatbot

Chattez avec Graph Search

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

Exploring High-Performance and Energy-Efficient Architectures for Edge AI-Enabled Applications

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures