Publication
This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.
Jacques Fellay, Flavia Aurelia Shoko Hodel
Didier Trono, Priscilla Turelli, Sandra Eloise Kjeldsen, Evaristo Jose Planet Letschert, Filipe Amândio Brandão Sanches Vong Martins, Florian Huber, Cyril David Son-Tuyên Pulver, Olga Marie Louise Rosspopoff, Romain Forey, Joana Carlevaro Fita