Remotely powered addressable UHF RFID integrated system

This paper presents a fully integrated remotely powered and addressable radio frequency identification (RFID) transponder working at 2.45 GHz. The achieved operating range at 4 W effective isotropically radiated power (EIRP) base-station transmit power is 12 m. The integrated circuit (IC) is implemented in a 0.5 "m silicon-on-sapphire technology. A state-of-the-art rectifier design achieving 37% of global efficiency is embedded to supply energy to the transponder. The necessary input power to operate the transponder is about 2.7 μW. Reader to transponder communication is obtained using on-off keying (OOK) modulation while transponder to reader communication is ensured using the amplitude shift keying (ASK) backscattering modulation technique. Inductive matching between the antenna and the transponder IC is used to further optimize the operating range. © 2005 IEEE.

Analysis and optimization of passive UHF RFID systems

Jari-Pascal Curty

Radio Frequency IDentification (RFID) is an automatic identification method, relying on storing and remotely retrieving data using devices called RFID tags or transponders. An RFID tag is a small object that can be attached to or incorporated into a product, animal or person. RFID tag contains antenna to enable it to receive and respond to Radio-Frequency (RF) queries from an RFID reader or interrogator. Passive tags require no internal power source, whereas active tags require a power source. As of today (2005), the ubiquitous computing and ambient intelligence ideas are making their way. In order for these to become a reality, a number of key technologies are required. Briefly, these technologies need to be sensitive, responsive, interconnected, contextualised, transparent and intelligent. RFID is such a technology and more particularly passive RFID tags. But, in order to deliver the necessary characteristics that could trigger ambient intelligence, there are some challenges that need to be addressed. Remote powering of the tags is probably the most important. Issues concerning the antenna-tag interface, as well as the rectifier design, that allows the RF signal to be converted to Direct Current (DC) are in pole position. Secondly, the communication link and the reader should be optimized. The RF signal that contains the tag data suffers from a power of four decay with the distance between tag and reader. As a result, both the reader sensitivity and the tag backscattered power efficiency have to be maximized. Long-range powering, as well as sufficient communication quality, are the guidelines of this work. This research project proposes a linear two-port model for an N-stage modified-Greinacher full wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameters values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. Also presented in this work is an experimental procedure to measure how the impedance modulation at the tag side affects the signal at the reader. The method allows the tag designer to efficiently predict the effect of modulator design at system level and gives an useful instrument to choose the most appropriate impedances. Finally, the design of a fully integrated remotely powered and addressable RFID tag working at 2.45 GHz is described. The achieved operating range at 4 W Effective Isotropically Radiated Power (EIRP) reader transmit power is 12 m. The Integrated Circuit (IC) is implemented in a 0.5 μm silicon-on-sapphire technology. A state of the art rectifier design achieving 37% of global efficiency is embedded to supply energy to the transponder. Inductive matching and a folded-dipole antenna are key elements to achieve these performances. The necessary input power to operate the transponder is about 2.7 μW.

EPFL2006

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Efficiency enhancement and frequency-tunable capability in linear CMOS RF power amplifiers for wireless applications

Paulo Augusto Dal Fabbro

This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technology, each one addressing a different aspect. With respect to efficiency enhancement, a dynamic supply RF power amplifier was realized. The circuit was designed for an operating frequency of 5.2 GHz, but measurements were also performed at 2.4 GHz. The integrated circuit includes a class A amplifier and a high-efficiency, switched-mode modulator. It occupies an area of 1.35 mm2. Two-tone measurement results at 2.4 and 5.2 GHz showed that the system can deliver over 16 dBm (40 mW) linear output power with efficiencies of 22.7% and 12.6%, respectively. Compared to a constant 2.5 V supply operation, the power amplifier operating with the dynamic supply delivers higher linear output power. Moreover, a relative efficiency improvement of a factor of 2.3 at 2.4 GHz and of a factor of 1.6 at 5.2 GHz at low output power levels is achieved. OFDM measurements at 2.4 GHz demonstrated that for an EVM lower than 3% and for an equal output power of 11 dBm (12.6 mW), the absolute improvement in efficiency is over 3.2%. In this work we also propose a tunable impedance matching network for use in multiband RF power amplifiers. This novel network is based on coupled inductors. A frequency-tunable RF power amplifier using this network was designed for operation at 3.7 and 5.2 GHz. Simulation results for the complete system integrated in a CMOS technology showed good results. However, the frequency-tunable behavior could not be observed in the characterization of the integrated circuit because of the low coupling factor of the integrated coupled inductors. A hybrid implementation using the integrated CMOS power amplifier, a discrete commercial RF transformer and a discrete bipolar transistor to control the current in the secondary winding of the transformer was carried out. The circuit was designed for operation at 200 and 300 MHz. The measurements have shown that at 200 MHz a relative improvement in efficiency of a factor of 1.4 was achieved. Moreover, less distortion was generated with the proposed tunable output matching network. The hybrid implementation allowed us to demonstrate the feasibility of the frequency-tunable RF power amplifier based on coupled inductors.

EPFL2009