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Dynamic feature selection for hardware prediction

Publications associées (21)

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STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

Predicting User-Cell Association in Cellular Networks from Tracked Data

Jean-Yves Le Boudec

We consider the problem of predicting user location in the form of user-cell association in a cellular wireless network. This is motivated by resource optimization, for example switching base transceiver stations on or off to save on network energy consump ...

Springer Verlag2009

Temporal instruction fetch streaming

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...

2008

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by “downsizing” hardware resources that are u ...

2004

Accurate and complexity-effective spatial pattern prediction

Babak Falsafi

Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixed cache line sizes to balance the exploitation of spatial and temporal locality, a ...

2004

Dynamic Data Dependence Tracking and Its Application to Branch Prediction

Lei Chen

To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to improving ILP is data dependences among instructions. If data dep ...

2003

Improving Application Performance by Dynamically Balancing Speed and Complexity in a GALS Microprocessor

2003

Using Cohort-Scheduling to Enhance Server Performance

James Richard Larus

A server application is commonly organized as a collection of concurrent threads, each of which executes the code necessary to process a request. This software architecture, which causes frequent control transfers between unrelated pieces of code, decrease ...

Usenix2002

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Babak Falsafi

Set-associative caches achieve low miss rates for typical applications but result in significant energy dissipation. Set-associative caches minimize access time by probing all the data ways in parallel with the tag lookup, although the output of only the m ...

2001

Memory sharing predictor: the key to a speculative coherent DSM

Babak Falsafi

Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and timely invoking the necessary coherence actions, a DSM can hide much of the re ...

1999