PyNEST: a convenient interface to the NEST simulator
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Using a first-principles approach, we study the incorporation of nitrogen at the Si(001)-SiO2 interface by calculating N Is core-level shifts for several relaxed interface models. The unusually large shift with oxide thickness of the principal peak in phot ...
Transactional memory (TM) is expected to become a widely used parallel programming paradigm for multi-core architectures. To reach this goal, we need tools that do not only help develop TMs, but also test them and evaluate them on a wide range of workloads ...
The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer’s coordination methodology is cons ...
Institute of Electrical and Electronics Engineers2010
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identical instruction streams is challenging because redundant cores operate indepe ...
We propose and demonstrate a reconfigurable tunable encoder for two-dimensional time–wavelength optical code division multiple access (OCDMA). This encoder is capable of creating 2D codes with variable code weight, enabling differentiated service provision ...