Emulation-Based Transient Thermal Modeling of 2D/3D Systems-on-Chip with Active Cooling
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In this paper we present the manner the POEtic chip can be used to rapidly prototype systems. This chip, currently in test phase, is a system-on-chip containing a microprocessor and a reconfigurable array. Spe- cial features allow to dynamically create dat ...
Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of ...
Institute of Electrical and Electronics Engineers2000
The network-on-chip paradigm is an emerging paradigm that effectively addresses and presumably can overcome the many on-chip interconnection and communication challenges that already exist in today's chips or will likely occur in future chips. Effective on ...
Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular ...
The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) ar ...
Institute of Electrical and Electronics Engineers2005
