Publications associées à OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

IEEE2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programmi ...

2022

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Shabnam Sheikhha

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

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OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Inter-actions parallel execution on GPU from high-level dataflow synthesis

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

From C/C plus plus Code to High-Performance Dataflow Circuits

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Resource Sharing in Dataflow Circuits

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Essays on adaptation to rare disasters

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Graph Chatbot

Chattez avec Graph Search

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Resource Sharing in Dataflow Circuits

Essays on adaptation to rare disasters

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

From C/C plus plus Code to High-Performance Dataflow Circuits

Buffer Placement and Sizing for High-Performance Dataflow Circuits