Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

This paper presents a contribution to the development of rapid prototyping tools based on data-flow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cases. Moreover, this paper presents the novel concept of the automatic synthesis of interfaces based on dataflow description. Such “generic” interfaces include an embedded microprocessor, which enables using a vide variety of interfaces already available as optimized libraries from the FPGA manufacturers. The different design cases described have been tested and validated on different platforms. The results of the work show the flexibility and generality of the proposed wrapper methodology that is described in the paper.

Generation of Hardware/Software Systems Based on CAL Dataflow Description

Julien Dubois, Marco Mattavelli, Romuald Mosqueron, Richard Thavot

This chapter presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The chapter also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results of the assessment show that flexibility, genericity and generality are attractive.

Springer2010

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Christophe Lucarz, Marco Mattavelli, Ghislain Roquier

The possibility of specifying both SW and HW components using the same language is a very attractive design approach. However, despite the efforts spent for implementing such approach using common programming languages such as C and C++, it has not yet shown to be viable and efficient for complex design. The main reason is the difficulty of expressing architectural properties at the level of a common description, difficulty that finally results into the failure of synthesizing efficient HW and efficient parallel SW. This is not the case for dataflow programming that is well- suited to the description of complex real-world computational systems that may contain appreciable amounts of concurrency. A CAL [1, 2] dataflow program is a collection of actors connected by lossless first-in/first-out (FIFO) communication channels, through which they exchange packets of data called tokens. Each actor executes in a sequence of steps, during which it can (1) consume input tokens, (2) produce output tokens, (3) modify its own local state. Actors strictly encapsulate their state, i.e. they cannot directly use or modify the state of other actors. Consequently, executing actors concurrently does not cause race conditions on any state variables, which makes dataflow an excellent (and scalable) parallel programming model. This in turn is key to the generation of efficient HW and SW implementations. This demonstration presents an integrated environment that embeds the synthesis tool that translates a CAL-based dataflow specification into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed by a processor and a FPGA platform just by annotating the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processing systems such as video codecs. As a case study, the demonstration provides the analysis and validation of different SW and HW partitioning of a MPEG-4 Simple Profile decoder.

IEEE2009

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

Endri Bezati, Marco Mattavelli

The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity for extensive design-space exploration, but they do raise the problem of efficient automatic synthesis to hardware and software. This paper presents a tool called Xronos that efficiently synthesizes RVC-CAL programs to an RTL-level hardware description and significantly improves on previous efforts in both quality of the resulting implementation and synthesis speed. By directly supporting all the features of the RVC-CAL language, it translates unmodified standard MPEG reference code to a functioning hardware implementation. The paper describes the essential processing architecture of Xronos, the differences from other related approaches and experimental results that show Xronos to produce faster and smaller implementations, while at the same time significantly reducing synthesis times.

2013

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Christophe Lucarz, Marco Mattavelli, Ghislain Roquier

IEEE2009