A Low-Power, Low Data-Rate, Ultra-Wideband Receiver Architecture for Indoor Wireless Systems

Abstract—In this paper, a novel architecture for a low data-rate, low power consumption Impulse Radio (IR) Ultra- Wideband (UWB) receiver is presented in which the received UWB signal is downconverted to a given intermediate frequency (IF) rather than at baseband. This way, the requirement to implement two separate paths for the in-phase and the quadrature components is removed and the power consumption can be reduced. From the IF, the signal is converted to the digital domain by a set of 24 Redundant Signed Digit (RSD) Analog to Digital Converters (ADCs) working at the pulse repetition rate. The digitized signal is then correlated with a predefined template prior to be fed to the bit detector. The trade-offs for the selection of the IF are highlighted and the BER performance of the proposed receiver is evaluated using simulations in 802.15.3a multipath channels. The expected power consumption for the implementation of the receiver using a CMOS process is also provided.

Low-power and low-voltage delta-sigma analog-to-digital converters for digital radio in standard CMOS technology

Nicola Scolari

The transceivers of a wireless sensor network (WSN) have to fulfill the low-power and low-voltage constraints. The WiseNET project has already proven that it is possible to design a receiver working at 1V and consuming less than 2mW. However this transceiver is using OOK and wideband FSK modulations, which have a very poor spectral efficiency. A more complex modulation scheme is therefore needed, which requires an ADC in order to demodulate the signal in the digital domain. The ADC is then becoming the main bottleneck if the low-power consumption is targeted. This thesis aims at studying a next generation WiseNET transceiver using a more spectral efficient phase modulation scheme, particularly the new IEEE 802.15.4 standard, and it focuses on the design of a low-power and low-voltage ADC. The choice of the best receiver architecture depends on many factors, among which the power consumption, the integration suitability, the image rejection, the flicker and quantization noise, etc. Several architectures are analyzed in order to identify the trade-offs and select the most suitable for the IEEE 802.15.4 standard, i.e. a low-IF receiver with a quadrature band-pass ΔΣ modulator. From these considerations, a 2nd-order continuous-time quadrature band-pass ΔΣ modulator was implemented in a 0.18μm standard digital process. The design is focused on the constraints of low power consumption, low supply voltage and low complexity imposed by WSN. The availability of I and Q signals in the low-IF receiver enables a quadrature architecture, which allows to combine signal filtering, image rejection and quantization noise reduction. A continuous-time Gm-C implementation further combines the anti-alias function within the ADC and allows to achieve the 1V operation. The quadrature ΔΣ modulator is clocked at 72MHz and the center frequency is set to 3.75MHz with a bandwidth of 3MHz. The maximum measured signal-to-noise ratio is 36dB and the power consumption is only 450μW under 1V.

EPFL2007

A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

Cyril Botteron, Frédéric Chastellain, Pierre-André Farine, Saeed Ghamari, Christian Robert

An Analog to Digital Converter (ADC) using the low duty-cycle nature of pulse-based Ultra Wide-Band (UWB) communications to reduce its power consumption is proposed. Implemented in CMOS 180 nm technology, it can capture a 5 ns window at 4 GS/s each 100 ns, which corresponds to the acquisition of one UWB pulse at the pulse repetition rate of 10 mega pulses per second (Mpps). By using time-interleaved Redundant Signed Digit (RSD) ADCs, the complete ADC occupies only 0.15 mm2 and consumes only 1.4 mW from a 1.8 V power supply. The ADC can be operated in two modes using the same core circuits (operational transconductance amplifier, comparators, etc.). The first mode is the standard RSD doubling mode, while the second mode allows improving the signal-to-noise ratio by adding coherently the transmitted pulses of one symbol. For example, for audio applications, a 300 kbps data rate and processing gain up to 15 dB can be achieved at a clock frequency of 10 MHz.

2014

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Low-power and low-voltage delta-sigma analog-to-digital converters for digital radio in standard CMOS technology

Nicola Scolari

EPFL2007

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

EPFL2007