An Experimental Platform for an Indoor Location and Tracking System

In this paper, an experimental platform for indoor location and tracking using ultra wideband (UWB) impulse radio signals is presented and its performance measured. The platform has been developed entirely using standard electronic components that are commercially available. As principal goal, the experimental platform has been designed to allow a rapid performance evaluation for various system architectures and signal processing algorithms. Hence, the platform is as versatile as possible while remaining optimized for accurate location estimation. To meet these targets, the UWB receivers are implemented using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA). The ADC acquires directly the received radio frequency signal. The FPGA performs the required signal processing in real time and estimates the time of arrivals (TOAs) of the received pulses. The TOAs are transferred to a personal computer (PC), where the location of the transmitter is calculated. After the description of the hardware and the algorithms, the outcomes of a measurement campaign in a laboratory environment and the accuracy of the location system are presented.

UWB-based Local Positioning System: from a small-scale Experimental Platform to a large-scale Deployable System

Cyril Botteron, Pierre-André Farine, Christian Robert, Phillip Tomé

A few years ago an experimental platform was designed and built in order to demonstrate the feasibility of Ultra-Wideband (UWB) technology applied to indoor positioning. This small-scale demonstrator proved to be a valuable research tool with the flexibility to study, test and assess the performance of various system architectures and signal processing algorithms. Based on this successful experience, the current follow-up R&D project aims to extend the research to other topics by pursuing two main objectives: a) designing and building a large-scale deployable UWB-based Local Positioning System (LPS), including its installation, calibration and operational testing in a real industrial environment; b) conceiving and developing Application Specific Integrated Circuits (ASICs) to target cost-competitive solutions. This paper addresses the main design issues analyzed during the requirements definition phase for this large-scale deployable LPS, considering that the new system should inherit whenever possible the design features already present in the small-scale experimental platform.

2010

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

EPFL2007