Frequency-domain analysis of ground electrodes buried in an ionized soil when subjected to surge currents: A MoM–AOM approach
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We present an experimental and theoretical analysis of the self-and cross-Kerr effect of extended plasma resonances in Josephson junction chains. We calculate the Kerr coefficients by deriving and diagonalizing the Hamiltonian of a linear circuit model for ...
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This communication extends a previously reported analytical circuit that models the plane wave scattering by 2-D arrays of planar patches/apertures embedded in a layered media. In this extension, it is assumed that the current/electric field spatial profil ...
The adoption of the best available estimate for the stator Leakage reactance is the first step in several equivalent circuit of synchronous machine parameter estimation. However, there is no specific test for its direct measurement. This paper presents a s ...
An equivalent-network model is here proposed to characterize two-dimensional planar periodic arrays of arbitrary scatterers/apertures embedded in a layered environment. The model is an extension of the approach previously developed by some of the authors, ...
Institute of Electrical and Electronics Engineers2015
Protection of tapped transmission lines with grounded neutrals has been always a challenging problem, usually resulting in compromise solutions. This type of lines may be protected by pilot relaying requiring dedicated and reliable telecommunication links. ...
The paper deals with the calculation of transient currents and voltages along curved wire structures buried in a lossy ground using the generalized Telegrapher's equations. The influence of a lossy half space is taken into account by the simplified reflect ...
Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...
Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed und ...