Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

Signal processing designs are becoming increasingly complex with demands for more advanced algorithms. Designers are now seeking high-level tools and methodology to help manage complexity and increase productivity. Recently, CAL dataflow language has been specified which is capable of synthesizing dataflow description into RTL codes for hardware implementation, and based on several case studies, have shown promising results. However, no work has been done on global network analysis, which could increase the optimization space. In this paper, we introduce methodologies to analyze and optimize CAL programs by determining which actions should be parallelized, pipelined, or refactored for the highest throughput gain, and then providing tools and techniques to achieve this using minimum resource. As a case study on the RVC MPEG-4 SP Intra decoder for implementation on Virtex-5 FPGA, experimental results confirmed our analysis with throughput gain of up to 3.5x using relatively-minor additional slice compared to the reference design.

Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

Ab Al Hadi Bin Ab Rahman, Ihab Mostafa Amin Mohamed Amer, Hossam Amer, Christophe Lucarz, Marco Mattavelli

The specification of complex signal processing systems in hardware by means of HDL is no longer the appropriate way since they are known to be time consuming to design, and less flexible to extend features. Recently, \CAL dataflow language was specified to increase productivity and scalability, with ability to synthesize to HDL for hardware implementation. In this paper, a new methodology to improve throughput of dataflow-based hardware designs is given by analyzing \CAL programs using the profiling tool. As a case study, we analyzed the RVC MPEG-4 SP Intra decoder and found that the texture decoding part has the highest improvement factor. We have also introduced the luminance texture splitting technique as the improvement method by increasing the level of parallelism in the decoder. Experimental results of implementation on Virtex-5 FPGA confirmed our analysis with throughput in- crease of up to 50.5% with only 4.3% additional slice.

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

High-level synthesis of dataflow programs for heterogeneous platforms

Endri Bezati

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for complex systems, raising the level of abstraction does not necessarily come at a cost in terms of performance or resource requirements. As a matter of fact, high-level synthesis tools supporting such a high abstraction often rival and on occasion improve low-level design. In spite of these successes, high-level synthesis still relies on programs being written with the target and often the synthesis process, in mind. In other words, imperative languages such as C or C++, most used languages for high-level synthesis, are either modified or a constrained subset is used to make parallelism explicit. In addition, a proper behavioral description that permits the unification for hardware and software design is still an elusive goal for heterogeneous platforms. A promising behavioral description capable of expressing both sequential and parallel application is RVC-CAL. RVC-CAL is a dataflow programming language that permits design abstraction, modularity, and portability. The objective of this thesis is to provide a high-level synthesis solution for RVC-CAL dataflow programs and provide an RVC-CAL design flow for heterogeneous platforms. The main contributions of this thesis are: a high-level synthesis infrastructure that supports the full specification of RVC-CAL, an action selection strategy for supporting parallel read and writes of list of tokens in hardware synthesis, a dynamic fine-grain profiling for synthesized dataflow programs, an iterative design space exploration framework that permits the performance estimation, analysis, and optimization of heterogeneous platforms, and finally a clock gating strategy that reduces the dynamic power consumption. Experimental results on all stages of the provided design flow, demonstrate the capabilities of the tools for high-level synthesis, software hardware Co-Design, design space exploration, and power optimization for reconfigurable hardware. Consequently, this work proves the viability of complex systems design and implementation using dataflow programming, not only for system-level simulation but real heterogeneous implementations.

EPFL2015

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

Ab Al Hadi Bin Ab Rahman, Endri Bezati, Marco Mattavelli, Anatoly Prihozhy

This paper introduces a new methodology for pipeline synthesis with applications to data flow high-level system design. The pipeline synthesis is applied to dataflow programs whose operators are translated into graphs and dependencies relations that are then processed for the pipeline architecture optimization. For each pipeline-stage time, a minimal number of pipeline stages are first determined and then an optimal assignment of operators to stages is generated with the objective of minimizing the total pipeline register size. The obtained "optimal" pipeline schedule is automatically transformed back into a dataflow program that can be synthesized to efficient hardware implementations. Two new pipeline scheduling: "least cost search branch and bound" and a heuristic technique have been developed. The first algorithm yields global optimum solutions for middle size designs, whereas the second one generates close-to-optimal solutions for large designs. Experimental results on FPGA designs show that the total pipeline register size gain in a range up to 4.68x can be achieved. The new algorithms overcome the known downward and upward direction dataflow graph traversal algorithms concerning the amount of pipeline register size by up to 100% on average.

Ieee-Inst Electrical Electronics Engineers Inc2015

High-level synthesis of dataflow programs for heterogeneous platforms

Endri Bezati

EPFL2015