Monolithic integration of Si nanowires with metallic electrodes: NEMS resonator and switch applications

The challenge of wafer-scale integration of silicon nanowires into microsystems is addressed by developing a fabrication approach that utilizes a combination of Bosch-process-based nanowire fabrication with surface micromachining and chemical-mechanical-polishing-based metal electrode/contact formation. Nanowires up to a length of 50 mu m are achieved while retaining submicron nanowire-to-electrode gaps. The scalability of the technique is demonstrated through using no patterning method other than optical lithography on conventional SOI substrates. Structural integrity of double-clamped nanowires is evaluated through a three-point bending test, where good clamping quality and fracture strengths approaching the theoretical strength of the material are observed. Resulting devices are characterized in resonator and switch applications-two areas of interest for CMOS-compatible solutions-with all-electrical actuation and readout schemes. Improvements and tuning of obtained performance parameters such as resonance frequency, quality factor and pull-in voltage are simply a question of conventional design and process adjustments. Implications of the proposed technique are far-reaching including system-level integration of either single-nanowire devices within thick Si layers or nanowire arrays perpendicular to the plane of the substrate.

A Monolithic Approach to Downscaling Silicon Piezoresistive Sensors

Yusuf Leblebici, Mohammad Nasr Esfahani

Multi-scale integration remains the primary challenge in the fabrication of miniature piezoresistive sensors, as the co-fabrication of a silicon nanowire along with a microscale shuttle is the main architecture facilitating high-sensitivity transduction. The efforts in this field are marred by the lack of batch techniques compatible with semiconductor manufacturing. A technology is introduced here that leads to the fabrication of a piezoresistive silicon nanowire sharing the same single-crystalline device layer of a thick silicon-on-insulator wafer as the microscale component. The approach is based on a combination of high-resolution lithography with a two-stage etching process. The demonstration is carried out by spanning an electrostatic comb-drive actuator and a micromechanical amplifier by a single nanowire. A gage factor range of 135-145 is obtained, corresponding to an almost 20% resistance change for a nanowire strain of 1.26 x 10(-3). The technique is shown to generate a two-order-of-magnitude scale difference within the same silicon crystal. It also provides ease of electrical access to the nanowire, as the nanowire does not remain buried underneath the thick micromechanical system. With the associated lack of high-temperature processes and its CMOS-compatibility, the technique is a promising enabler for future miniaturized piezoresistive sensors. [2017-0007]

Institute of Electrical and Electronics Engineers2017

Piezoresistivity characterization of silicon nanowires through monolithic MEMS

Yusuf Leblebici, Mohammad Nasr Esfahani

This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-μm-thick MEMS on the same silicon-on-insulator (SOI) wafer. MEMS is designed in the form of a characterization platform with an electrostatic actuator and a mechanical amplifier spanned by a single Si NW. This integrated platform is utilized for the successful measurement of Si NW piezoresistive gauge factor (GF) under a uniform uniaxial stress. Available techniques in this field include: Indirect (substrate) or direct (actuator) bending of Si NW necessitating rigorous models for the conversion of load to stress, inanomanipulation and attachment of Si NW on MEMS, a non-monolithic technique posing residual stress and alignment issues, and heterogeneous integration with separate Si layers for Si NW and MEMS, where a single SOI is not sufficient for the end product. Providing a monolithic solution to the integration of micro and nanoscale components, the presented technique successfully addresses the shortcomings of similar studies. In addition to providing a solution for electromechanical characterization, the technique also sets forth a promising pathway for multiscale, functional devices produced in a batch-compatible fashion, as it facilitates co-fabrication within the same Si crystal.

2017

Carbon Nanotube Electromechanical Devices for Radio Frequency Applications

Anupama Arun

Carbon nanotubes (CNT) have been investigated extensively in the recent years for application in nano-electromechanical systems (NEMS). CNTs have extraordinary electrical and mechanical properties. They are stiff, with low density, high electrical conductivity and hence are the ideal candidates for NEMS. Beyond miniaturization, NEMS can also offer better performance than its predecessor micro-electro mechanical systems (MEMS). NEMS find application in ultra-sensitive mass and force detection, RF signal processing, low power operated switches with fast switching speeds, to name a few. Despite tremendous promise the main challenge in CNT research has been the fabrication technology to realize CNT based devices with precise control of location and properties of CNT. CNTs are one-dimensional structures with high aspect ratio. To realize devices for practical application with high signal-to-noise-ratio, it becomes necessary to operate many of them in parallel. To fabricate an array of CNTs in parallel posse's additional challenge to the fabrication technology but the resulting structures could provide benefits compared to both NEMS fabricated with one dimensional structures and MEMS. During the course of this thesis, different fabrication technologies were investigated to realize CNT array based devices. A self assembly method, dielectrophoresis and CVD growth were optimized to realize CNT based devices. A novel technique using a modified dielectrophoresis method was setup to be able to trap a single CNT. A CNT crossed junction was fabricated using the same. The electrical properties of the junction were studied. A Suspended Gate CNT array Field Effect Transistor (SG-CNT-FET) based resonator was demonstrated for the first time. SG-CNT-FET combines the excellent mechanical properties of CNTs with the gain of the solid state field effect transistor. The use of an array configuration ensures better signal-to-noise-ratio compared to device implemented with a single CNT. A novel process flow combining the fabrication of a FET and deposition of CNTs by dielectrophoresis was developed. Resonance frequency up to 150 MHz with a quality factor of approximately 50 was obtained. The resonance frequency is tuneable by modulating the tension in the CNT array by applying a DC bias. Dependence of the resonance frequency on the applied bias has been studied under the frame work of a continuum mechanics model. The small signal circuit parameters have been extracted, enabling future circuit design. Vertically grown CNT array were grown on metal lines to realize a tuneable MEM capacitor. The CNT array forms a membrane like structure which can be electro-statically actuated. Morphological and electrical characterizations were performed on the fabricated devices. DC characterization revealed the pull-in behavior like conventional MEMS. The Young's modulus of the grown vertical CNT array was extracted from the measured pull-in voltage. An effective Young's modulus of 30-100 MPa was obtained. An equivalent electrical model was developed to extract the capacitance from the S-parameters measurements, measured up to 6 GHz. The model was validated by ADS circuit simulations. A voltage controlled oscillator at 2.45 GHz has been implemented using the thus realized tuneable MEM capacitor.

EPFL2010

Carbon Nanotube Electromechanical Devices for Radio Frequency Applications

Anupama Arun

EPFL2010