Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

The performance of a standard MOSFET degrades with the increase in temperature, impacting the power consumption of the device. In this paper, we report the opposite trend, which is reflected in an improvement of main performance factors in ferroelectric FETs (Fe-FETs), when the temperature is increased. We explain our results by Landau's theory, which is also used to develop and validate an analytical model of ferroelectric capacitance. In order to validate the model, we fabricate and dc characterize a fully depleted silicon-on-insulator transistor with 10-nm SiO2 and 40 nm of vinylidene fluoride trifluorethylene P(VDF-TrFE) as a gate stack at different temperatures, ranging from 300 to 400 K. The transconductance and the subthreshold swing of a Fe-FET show a maximum and a minimum in correspondence to the Curie temperature of the ferroelectric, respectively. The proposed model and extraction is valid for any type of ferroelectric materials and Fe-FETs. Finally, this paper demonstrates that the performance degradation in a standard MOSFET (e. g., transconductance and subthreshold swing) at a high temperature of operation could be reduced or even suppressed in a Fe-FET if the Curie temperature of the gate stack is appropriately designed.

The Curie temperature as a key design parameter of ferroelectric Field Effect Transistors

Didier Bouvet, Mihai Adrian Ionescu, Livio Lattanzio, Giovanni Antonio Salvatore

Interest in Ferroelectric FETs originates from their potential as non-volatile memories and, more recently, as abrupt switches. In this work, we focus on the role of the Curie temperature of the gate stack on the performance of Fe-FETs. The proposed study is based on thin film SOI Fe-FETs using organic ferroelectric gate stacks (45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO2). The device static characteristics are investigated from 25°C up to 155°C, from ferroelectric to paraelectric phase. We report a maximum of the transconductance at the Curie Temperature (Tc), where the ferroelectric material loses its spontaneous polarization and the transistor loses its hysteresis. The reported increase of current and transconductance with the temperature up to Tc are in contrast with the behavior in any conventional MOSFET. The experimental results are supported by an appropriate analytical model. We suggest that the Curie Temperature of the gate stack is a key design parameter for the use of Fe-FETs as non-hysteretic switches with increased on-current, close or beyond Tc, or as memory cells, in the hysteretic domain, much below Tc.

IEEE2010

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

EPFL2012