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ECC2K-130 on Cell CPUs

Publications associées (34)

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High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

This paper presents software implementation speed records for modular multiplication arithmetic on the synergistic processing elements of the Cell broadband engine (Cell) architecture. The focus is on moduli which are of special interest in elliptic curve ...

Springer Berlin Heidelberg2010

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Marco Mattavelli, Christophe Lucarz, Ghislain Roquier

Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer ...

2010

Montgomery Multiplication on the Cell

Joppe Willem Bos, Marcelo Kaihara

A technique to speed up Montgomery multiplication targeted at the Synergistic Processor Elements (SPE) of the Cell Broadband Engine is proposed. The technique consists of splitting a number into four consecutive parts. These parts are placed one by one in ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

System for generating computer processor

A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor tha ...

2010

Processor Speed Control with Thermal Constraints

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

We consider the problem of adjusting speeds of multiple computer processors, sharing the same thermal environment, such as a chip or multichip package. We assume that the speed of each processor (and associated variables such as power supply voltage) can b ...

2009

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeo ...

2007

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Eric Vittoz, Yusuf Leblebici, Zeynep Toprak Deniz

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing ...

2007

Multi-unit global energy management and optimization for network-on-chip applications

Zeynep Toprak Deniz

The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...

EPFL2006

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006