Methodology for the Hardware/Software Co-Design of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa, 2011
Article de conférence

New generations of multi-core processors and reconfigurable hardware platforms are expected to provide a dramatic increase of processing capabilities. However, one obstacle for exploiting all the promises of such new platforms is the legacy of current applications and the development methodologies used, which is deeply rooted in a sequential way of thinking. A paradigm shift is necessary at all levels of application development to yield portable and efficient implementations, capable of exploiting the full potential of such platforms. Dataflow programming is an alternative approach that address the problem of providing portable and scalable parallel applications. Dataflow programming is able to explicitly expose the intrinsic parallelism of applications. This paper presents a hardware/software co-design methodology that starting from a unique dataflow program enables, by the direct synthesis of both hardware (HDL) and software components (C/C++), to map a signal processing application onto heterogeneous systems architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of the MPEG-4 Simple Profile decoder onto an heterogeneous platform are also provided to show the capabilities and flexibility of the approach.

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Marco Mattavelli, Ghislain Roquier, Richard Thavot
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa, 2011
Article de conférence

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https://infoscience.epfl.ch/record/173455?ln=fr

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Dataflow programming

In computer programming, dataflow programming is a programming paradigm that models a program as a directed graph of the data flowing between operations, thus implementing dataflow principles and arc

Microprocesseur multi-cœur

vignette|Un processeur quad-core AMD Opteron. vignette|L’Intel Core 2 Duo E6300 est un processeur double cœur. Un microprocesseur multi-cœur (multi-core en anglais) est un microprocesseur possédant p

Reconfigurable computing

Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics li

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

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Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

Ab Al Hadi Bin Ab Rahman, Ihab Mostafa Amin Mohamed Amer, Hossam Amer, Christophe Lucarz, Marco Mattavelli

The specification of complex signal processing systems in hardware by means of HDL is no longer the appropriate way since they are known to be time consuming to design, and less flexible to extend features. Recently, \CAL dataflow language was specified to increase productivity and scalability, with ability to synthesize to HDL for hardware implementation. In this paper, a new methodology to improve throughput of dataflow-based hardware designs is given by analyzing \CAL programs using the profiling tool. As a case study, we analyzed the RVC MPEG-4 SP Intra decoder and found that the texture decoding part has the highest improvement factor. We have also introduced the luminance texture splitting technique as the improvement method by increasing the level of parallelism in the decoder. Experimental results of implementation on Virtex-5 FPGA confirmed our analysis with throughput in- crease of up to 50.5% with only 4.3% additional slice.

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

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Actor Merging for Dataflow Process Networks

Jani Boutellier, Marco Mattavelli, Ghislain Roquier

Dataflow process networks provide a versatile model of computation for specifying signal processing applications in a platform independent fashion. This attractive feature of dataflow has lately been realized in dataflow programming tools that allow synthesizing the same application specification as both fixed hardware circuits and as software for programmable processors. However, in practice, the specification granularity of the dataflow program remains an arbitrary choice of the designer. Dataflow specifications of the same application with equivalent I/O behaviour can range from a single dataflow actor to a very fine grained network composed of elementary processing operations. A very fine grained dataflow specification might result into a high performance implementation when synthesized as hardware, but might perform poorly when executed on a programmable processor. This article presents actor merging as one solution for this performance portability problem of dataflow programs. In contrast to previous work around actor merging, this article presents a methodology that can merge also dynamic dataflow actors. To support these claims, results of experiments on several processing platforms and application examples ranging from telecommunications to video compression are reported.

Ieee-Inst Electrical Electronics Engineers Inc2015

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