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Asynchronous Broadcast on the Intel SCC using Interrupts

Publications associées (40)

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Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

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Mihai Letia

Recent trends have led hardware manufacturers to place multiple processing cores on a single chip, making parallel programming the intended way of taking advantage of the increased processing power. However, bringing concurrency to average programmers is c ...

EPFL2014

Consensus inside

Rachid Guerraoui, Maysam Yabandeh, Tudor Alexandru David

Scaling to a large number of cores with non-uniform communication latency and unpredictable response time may call for viewing a modern many-core architecture as a distributed system. In this view, the cores replicate shared data and ensure consistency amo ...

ACM Press2014

Consensus Inside

Rachid Guerraoui, Maysam Yabandeh, Tudor Alexandru David

2014

Achieving high-throughput State Machine Replication in multi-core systems

André Schiper, Nuno Filipe de Sousa Santos

The traditional architecture used by implementations of Replicated State Machines (RSM) does not fully exploit modern multi-core CPUs. This is increasingly the limiting factor in their performance, because network speeds are increasing much faster than the ...

Ieee2013

Parallelization of the distinct lattice spring model

Jiannong Fang, Liang Sun, Jian Zhao, Gaofeng Zhao

The distinct lattice spring model (DLSM) is a newly developed numerical tool for modeling rock dynamics problems, i.e. dynamic failure and wave propagation. In this paper, parallelization of DLSM is presented. With the development of parallel computing tec ...

Wiley-Blackwell2013

High-Performance RMA-Based Broadcast on the Intel SCC

André Schiper, Thomas Ropars, Omid Shahmirzadi, Darko Petrovic

Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel ...

2012

On the Performance of Software Transactional Memory

Aleksandar Dragojevic

The recent proliferation of multi-core processors has moved concurrent programming into mainstream by forcing increasingly more programmers to write parallel code. Using traditional concurrency techniques, such as locking, is notoriously difficult and has ...

EPFL2012

OLTP on Hardware Islands

Anastasia Ailamaki, Miguel Sérgio De Oliveira Branco, Pinar Tözün, Ippokratis Pandis, Danica Porobic

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

2012

The Complexity Of Early Deciding Set Agreement

Rachid Guerraoui, Bastian Pochon

In the k-set agreement problem, each processor starts with a private input value and eventually decides on an output value. At most k distinct output values may be chosen, and every processor's output value must be one of the proposed values. We consider a ...

Society for Industrial and Applied Mathematics2011