A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS
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A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...
The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis ...
The dielectric, electrical and structural properties of (1-x) (0.94Bi(1/2)Na(1/2)TiO(3)-0.06BaTiO(3))-xK(0.5)Na(0.5)NbO(3) (BNT-BT-xKNN) with x=0.09, 0.12, 0.15, and 0.18 were investigated as potential candidates for high-temperature capacitors with a work ...
In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy app ...
In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV ...
Springer, 233 Spring Street, New York, Ny 10013, United States2009
Cutting-edge CMOS neurochips, which consist of a Microelectrode Array (MEA) manufactured on top of CMOS circuitry, allow the recording of the electrical activity of neural networks in-vitro, and their stimulation. As CMOS technology continues to scale down ...
Based on analogy between the charging and discharging of humans' tolerance to overheating stimuli and that of charge in an electrical capacitor, this paper proposes a simple mathematical model for predicting overheating risk given a set of measured / simul ...
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
Based on results from a field survey campaign, this paper describes three new developments which have been integrated to provide for a comprehensive basis for the evaluation of overheating risk in offices. Firstly, a set of logistic regression equations ha ...
Based on results from a field survey campaign, this paper describes three new developments which have been integrated to provide for a comprehensive basis l'or the evaluation of overheating risk in offices. Firstly, a set of logistic regression equations h ...
Tsinghua University Press, Tsinghua University Press, Beijing 100084, Peoples R China2007