High-Level Synthesis of Dataflow Programs for Signal Processing Systems

The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity for extensive design-space exploration, but they do raise the problem of efficient automatic synthesis to hardware and software. This paper presents a tool called Xronos that efficiently synthesizes RVC-CAL programs to an RTL-level hardware description and significantly improves on previous efforts in both quality of the resulting implementation and synthesis speed. By directly supporting all the features of the RVC-CAL language, it translates unmodified standard MPEG reference code to a functioning hardware implementation. The paper describes the essential processing architecture of Xronos, the differences from other related approaches and experimental results that show Xronos to produce faster and smaller implementations, while at the same time significantly reducing synthesis times.

Software Code Generation for the RVC-CAL Language

Ghislain Roquier

The MPEG Reconﬁgurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a uniﬁed high-level speciﬁcation of current and future MPEG video coding technologies using dataﬂow models. In this framework, a decoder is built as a conﬁguration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are speciﬁed by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder conﬁguration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level speciﬁcation to efﬁcient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataﬂow program generates C code is validated against the original CAL description simulated using the Open Dataﬂow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Proﬁle decoder with different granularities are shown and discussed.

2009

Dataflow Programming for Systems Design Space Exploration for Multicore Platforms

Christophe Lucarz

Nowadays processing systems are asked to support increasing complex and demanding high-performance applications, especially in the signal processing and video processing domains. The design of these systems are becoming extremely challenging because of several factors. Among them the most relevant are: The advent of the parallel era The sequential general purpose processor era during which performance increased more than two-fold every year, is definitely over. There has been no further increase in leading edge processor performance for over five years now and all projects aimed at breaking the 4 GHz barrier have been canceled by the major processor manufacturers. So as to continue increasing the computing power of computer systems, manufacturers have to use several slower processing cores, while trying to minimize the power consumption. Sequential reference softwares are no longer adapted Up to now, sequential software have proven to be the winning approaches for exploiting the potential of each new generation of sequential processors. But the advent of the new parallel era changes the way systems are implemented and sequential reference software used as specification base are no longer appropriate starting points for designing complex systems. The increasing demanding functionality and performance In parallel with miniaturization and the necessity to handle severely resource-constrained implementation platforms, the functionality and complexity of large classes of systems continue to increase making them from many respects comparable to ordinary desktop personal computers. A mixture of different types of timing and quality constraints make overall system architecture design, resource allocation and scheduling more important and challenging topics than ever before. Additionally, the market asks companies to build efficient systems while using the minimum of resources as fast as possible. Due to the level of complexity reached by high-demanding digital systems, it is no longer reasonable to handle such systems at low levels of abstraction (e.g. VHDL/Verilog or C/C++). A solution to the problem is to higher the level of abstraction at which the design of such systems is performed. But for raising the level of abstraction, the need for portable parallelism is primordial so as to be able to implement all kind of systems on a wide range of target platforms. Thus, enabling portable parallelism should be a primordial requirement for the development of this level of abstraction and the associated methodology and tools. However, creating a new abstraction layer may incur in the risk of loosing contact with implementation details and accuracy necessary for achieving efficient implementations. This work focuses on tackling such problem by using the CAL data flow language as main abstraction at the basis of the design process. The attempt of solving such challenging problem consists in building an environment for enabling high level design space exploration of complex parallel application for seamless implementation on heterogeneous platforms using CAL. It includes the extraction of metrics (static analysis and profiling) with the intention to use them as a basis for partitioning and scheduling heuristics aiming at finding the most efficient partitions. It also implies developing methodologies for guiding designers in the optimization of the high level specifications. Finally, a holistic approach has been defined in form of a complete design flow starting from CAL specifications down to implementations. Where traditional approaches are faced to traverse, at each iteration of the design flow, all the levels of abstraction for testing a design solution, the use of CAL as an abstraction layer enables designers to separate clearly three domains of concerns that are made orthogonal: functionality, partitioning and implementation. The separation of these domains of concerns eases the design space exploration and leads to an increase in productivity in the design of complex systems. This work leads to the creation of several new design tools: (1) profiling tools which extracts metrics from CAL programs and (2) exploration tools which include partitioning and scheduling heuristics and performance evaluation. These tools have been implemented with the aim of guiding designers in the high level design space exploration of systems in order to achieve efficient implementation. A systematic methodology has been also elaborated and has been tested successfully on a real world applications. Thanks to the metrics extracted from the CAL program, the design bottlenecks of a MPEG-4 SP video decoder have been identified and removed at a high level of abstraction, leading to improvements up to 7 times faster implementation.

EPFL2011

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

Christophe Lucarz, Marco Mattavelli, Ghislain Roquier

The possibility of specifying both SW and HW components using the same language is a very attractive design approach. However, despite the efforts spent for implementing such approach using common programming languages such as C and C++, it has not yet shown to be viable and efficient for complex design. The main reason is the difficulty of expressing architectural properties at the level of a common description, difficulty that finally results into the failure of synthesizing efficient HW and efficient parallel SW. This is not the case for dataflow programming that is well- suited to the description of complex real-world computational systems that may contain appreciable amounts of concurrency. A CAL [1, 2] dataflow program is a collection of actors connected by lossless first-in/first-out (FIFO) communication channels, through which they exchange packets of data called tokens. Each actor executes in a sequence of steps, during which it can (1) consume input tokens, (2) produce output tokens, (3) modify its own local state. Actors strictly encapsulate their state, i.e. they cannot directly use or modify the state of other actors. Consequently, executing actors concurrently does not cause race conditions on any state variables, which makes dataflow an excellent (and scalable) parallel programming model. This in turn is key to the generation of efficient HW and SW implementations. This demonstration presents an integrated environment that embeds the synthesis tool that translates a CAL-based dataflow specification into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed by a processor and a FPGA platform just by annotating the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processing systems such as video codecs. As a case study, the demonstration provides the analysis and validation of different SW and HW partitioning of a MPEG-4 Simple Profile decoder.