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Leveraging Hardware Message Passing for Efficient Thread Synchronization

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Mechanisms for store-wait-free multiprocessors

Anastasia Ailamaki, Babak Falsafi

Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, programmers must choose from a spectrum of memory consistency models that reduce ...

2007

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui, Michal Kapalka

Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse-grained locking and easier to use than fine-grained locking. However, STM im ...

2007

Actors that Unify Threads and Events

Martin Odersky, Philipp Haller

There is an impedance mismatch between message-passing concurrency and virtual machines, such as the JVM. VMs usually map their threads to heavyweight OS processes. Without a lightweight process abstraction, users are often forced to write parts of concurr ...

Springer2007

Anonymous and Fault-Tolerant Shared-Memory Computing

Rachid Guerraoui, Eric Ruppert

The vast majority of papers on distributed computing assume that processes are assigned unique identifiers before computation begins. But is this assumption necessary? What if processes do not have unique identifiers or do not wish to divulge them for re ...

2007

Anonymous and fault-tolerant shared-memory computing

Rachid Guerraoui, Eric Ruppert

Springer, Springer-Verlag2007

Parallel depth first vs. work stealing schedulers on CMP architectures

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of off-chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlapp ...

2006

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui, Michal Kapalka

Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than coarse-grained locking and easier to use than fine-grained locks. However, STM implementatio ...

2006

Event-Based Programming without Inversion of Control

Martin Odersky, Philipp Haller

The actor computation model is especially suited for concurrent and distributed computations. Actors are basically concurrent processes which communicate through asynchronous message passing. When combined with pattern matching for messages, actor-based pr ...

2006

The Granularity of Soft-Error Containment in Shared-Memory Multiprocessors

Babak Falsafi

Concerns over rising soft-error rates in processor logic has led to numerous proposals for error tolerance mechanisms. In this paper, we examine the role of soft-error containment in a shared memory multiprocessor. We study a range of design alternatives b ...

2006

The Alpha of Indulgent Consensus

Rachid Guerraoui

This paper presents a simple framework unifying a family of consensus algorithms that can tolerate process crash failures and asynchronous periods of the network, also called indulgent consensus algorithms. Key to the framework is a new abstraction we intr ...

2006