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Making Pointer-Based Data Structures Cache Conscious

Publications associées (72)

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Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Exploration of Memory Hierarchy Configurations for Efficient Garbage Collection on High-Performance Embedded Systems

David Atienza Alonso

Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multiple applications that are dynamically launched by the user, which can produce ...

ACM Press2009

Dynamic Resource Allocation for Database Servers Running on Virtual Storage

Adrian Daniel Popescu, Daniel Lupei, Jin Chen

We introduce a novel multi-resource allocator to dynamically allocate resources for database servers running on virtual storage. Multi-resource allocation involves proportioning the database and storage server caches, and the storage bandwidth between appl ...

2009

Miss Rate Prediction across Program Inputs and Cache Configurations

Chen Ding

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets and all cache configurations. This pape ...

2007

Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeo ...

2007

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

ReCast: Boosting tag line buffer coverage in low-power high-level caches "for free"

Babak Falsafi

We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag set cache that filters a significant number of tag probes to the L2 tag array thus reducing power. The key contribution in ReCast is S-Shift, a simple indexin ...

2005

TRUSS: A Reliable, Scalable Server Architecture

Babak Falsafi

Traditional reliable servers require costly design changes to the processor, use custom system or application software, or cannot scale beyond a few processing elements. We present TRUSS, a family of server architectures providing reliable, scalable comput ...

2005

Miss Rate Prediction across All Program Inputs

Chen Ding

2003