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Amodernmanycore architecture can be viewed as a distributed system with explicit message passing to communicate between cores. Ensuring the consistency of shared state replicated over several cores is the key to the well functioning of such a system. Yet, ...
Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...
There is a rapid rise of multi-cores in recent hardware architectures. To exploit computational power of multi-core architectures, software should shift to be as concurrent as possible; and therefore should have concurrency control mechanisms. There are di ...
The advent of multicore CPUs has led to renewed interest in software routers built from commodity PC hardware. However, fully exploiting the parallelism due to multiple cores requires the ability to efficiently parallelize the delivery of packets to cores. ...
The combination of low cost clusters and multicore processors lowers the barrier for accessing massive amounts of computing power. As computational sciences advance, the use of in silico simulations to complement in vivo experiments promises parallel progr ...
Database engines face growing scalability challenges as core counts exponentially increase each processor generation, and the efficiency of synchronization primitives used to protect internal data structures is a crucial factor in overall database performa ...
Transactional memory (TM) is a promising paradigm for concurrent programming. Whereas the number of TM implementations is growing, however, little research has been conducted to precisely define TM semantics, especially their progress guarantees. This pape ...
There is an impedance mismatch between message-passing concurrency and virtual machines, such as the JVM. VMs usually map their threads to heavyweight OS processes. Without a lightweight process abstraction, users are often forced to write parts of concurr ...
Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed mem ...
A parallel algorithm for reordering the eigenvalues in the real Schur form of a matrix is presented and discussed. Our novel approach adopts computational windows and delays multiple outside-window updates until each window has been completely reordered lo ...