Publication
Novel Configurable Logic Block Architecture Exploiting Controllable-Polarity Transistors, invited paper
Concepts associés (29)
Reconfigurable computing
Reconfigurable computing is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the datapath itself in addition to the control flow. On the other hand, the main difference from custom hardware, i.e.
Field-programmable gate array
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together.
Fabrication des dispositifs à semi-conducteurs
thumb|upright=1.5|Évolution de la finesse de gravure des processeurs entre 1970 et 2017 La fabrication des dispositifs à semi-conducteur englobe les différentes opérations permettant l'élaboration de composants électroniques basés sur des matériaux semi-conducteurs. Entrent dans cette catégorie de composants à semi-conducteur, les composants discrets qui n'ont qu'une seule fonction comme les diodes et les transistors, et les circuits intégrés plus complexes, intégrant plusieurs composants, jusqu'à des milliards, dans le même boîtier.
Gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.
Programmable Array Logic
Programmable Array Logic (PAL) is a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor. PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.
Transistor à effet de champ à grille métal-oxyde
thumb|right|235px|Photographie représentant deux MOSFET et une allumette Un transistor à effet de champ à grille isolée plus couramment nommé MOSFET (acronyme anglais de metal-oxide-semiconductor field-effect transistor — qui se traduit par transistor à effet de champ à structure métal-oxyde-semiconducteur), est un type de transistor à effet de champ. Comme tous les transistors, le MOSFET module le courant qui le traverse à l'aide d'un signal appliqué sur son électrode nommée grille.
Programmable logic array
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gates for N input variables, and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms.
Circuit underutilization
Circuit underutilization also chip underutilization, programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standardized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or a CPLD. In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip.
Complex programmable logic device
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The main building block of the CPLD is a macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. Some of the CPLD features are in common with PALs: Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up.
Field-programmability
An electronic device or embedded system is said to be field-programmable or in-place programmable if its firmware (stored in non-volatile memory, such as ROM) can be modified "in the field", without disassembling the device or returning it to its manufacturer. This is often an extremely desirable feature, as it can reduce the cost and turnaround time for replacement of buggy or obsolete firmware. For example, a digital camera vendor could distribute firmware supporting a new image by instructing consumers to download a new firmware to the camera via a USB cable.