Publications associées à A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

Pierre-André Farine, Steve Tanner, Urs Alexander Müller

In this paper, the design of a low-noise amplifier (LNA) for a 32x32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10 μVrms, respectively, at a bandwidth of 66 kHz. The LNA consumes less than 85 μW. The integrated of ...

2011

FPGA Design with Double-Gate Carbon Nanotube Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mohamed Haykel Ben Jamaa, Michele De Marchi

Double-gate carbon nanotube field effect transistors (DGCNTFETs) are novel devices showing an interesting property allowing to control the p- or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on ...

2011

Reliability in the Dark Silicon Era

Babak Falsafi

Information technology is now an indispensable pillar of a modern-day society, thanks to the proliferation of digital platforms in the past several decades. The demand on robust and economical data processing and storage, however, is growing faster than te ...

IEEE Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, CA 907202011

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

David Atienza Alonso, Ivan Beretta

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing perform ...

IEEE Press2010

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

David Atienza Alonso, Pablo Garcia del Valle

State-of-the-art devices in the consumer electronics market are relying more and more on Multi-Processor Systems-On-Chip (MPSoCs) as an efficient solution to meet their multiple design constrains, such as low cost, low power consumption, high performance a ...

Elsevier2010

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Giovanni De Micheli, David Atienza Alonso

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

Springer2010

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

Giovanni De Micheli, Mohamed Haykel Ben Jamaa, Michele De Marchi

In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambi ...

2010

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

David Atienza Alonso, Luca Benini, Srinivasan Murali

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

IEEE Press2009

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A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited)

EGRA: A Coarse Grained Reconfigurable Architectural Template

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

FPGA Design with Double-Gate Carbon Nanotube Transistors

Reliability in the Dark Silicon Era

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Improving FPGA Performance for Carry-Save Arithmetic

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Graph Chatbot

Chattez avec Graph Search

EGRA: A Coarse Grained Reconfigurable Architectural Template

Low-noise amplifier with sample & hold for high-density stimulation and recording of neural signals

FPGA Design with Double-Gate Carbon Nanotube Transistors

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Reliability in the Dark Silicon Era

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

Improving FPGA Performance for Carry-Save Arithmetic

Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications