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Leveraging Hardware Message Passing for Efficient Thread Synchronization

Publications associées (162)

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High-Performance RMA-Based Broadcast on the Intel SCC

André Schiper, Thomas Ropars, Omid Shahmirzadi, Darko Petrovic

Many-core chips with more than 1000 cores are expected by the end of the decade. To overcome scalability issues related to cache coherence at such a scale, one of the main research directions is to leverage the message-passing programming model. The Intel ...

2012

Addressing the ZooKeeper Synchronization Inefficiency

André Schiper, Babak Kalantari

In this paper we discuss the problem of synchronization in ZooKeeper, a fault-tolerant distributed coordination framework. One of the key features of ZooKeeper is to move away from blocking API such as locks, in order to avoid problems with slow or faulty ...

2012

Data Races vs. Data Race Bugs: Telling the Difference with Portend

George Candea, Cristian Zamfir, Baris Can Cengiz Kasikci

Even though most data races are harmless, the harmful ones are at the heart of some of the worst concurrency bugs. Alas, spotting just the harmful data races in programs is like finding a needle in a haystack: 76%-90% of the true data races reported by sta ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2012

Speculative Linearizability

Rachid Guerraoui, Viktor Kuncak, Giuliano Losa

Linearizability is a key design methodology for reasoning about implementations of concurrent abstract data types in both shared memory and message passing systems. It provides the illusion that operations execute sequentially and fault-free, despite the a ...

2011

The Complexity Of Early Deciding Set Agreement

Rachid Guerraoui, Bastian Pochon

In the k-set agreement problem, each processor starts with a private input value and eventually decides on an output value. At most k distinct output values may be chosen, and every processor's output value must be one of the proposed values. We consider a ...

Society for Industrial and Applied Mathematics2011

Model Checking of Distributed Algorithm Implementations

Maysam Yabandeh

It is notoriously difficult to develop reliable, high-performance distributed systems that run over asynchronous networks. Even if a distributed system is based on a well-understood distributed algorithm, its implementation can contain errors arising from ...

EPFL2011

Émulation de mémoire partagée en environnements distribués dynamiques

Vincent Gramoli

Most distributed systems are large-scale and dynamic. Communication has thus become a critical issue and the shared memory, which is a reliable paradigm of communication, allow distributed nodes to exchange information through read and write operations. In ...

2011

Deadlock Immunity

Horatiu Jula

Deadlock immunity is a property by which programs, once afflicted by a deadlock, develop resistance against future occurrences of that deadlock. We enable real applications to automatically achieve immunity against deadlock bugs involving mutex locks, sema ...

EPFL2011

Verification of STM on relaxed memory models

Rachid Guerraoui, Vasu Singh

Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed ...

Springer Verlag2011

Cache-Aware Lock-Free Concurrent Hash Tries

Martin Odersky, Aleksandar Prokopec

This report describes an implementation of a non-blocking concurrent shared-memory hash trie based on single-word compare-and-swap instructions. Insert, lookup and remove operations modifying different parts of the hash trie can be run independent of each ...

2011