Contact resistance effects in organic n-channel thin-film transistors

Organic thin-film transistors (TFTs) have undergone tremendous progress in the past few years. Their great potential in terms of mechanical flexibility, light weight, low-cost and large-area fabrication makes them promising candidates for novel electronic products, such as sensor arrays, radio-frequency identification tags and flexible displays. For the realization of these applications and to improve their performance it is necessary to miniaturize organic TFTs to dimensions of a few micrometers or even less. However, with such aggressive scaling, the device physics becomes more and more important. Especially the contact resistance at and close to the interface between the organic semiconductor and the source/drain metal limits the performance of the organic TFTs at miniaturized dimensions. In this thesis, the contact properties of bottom-gate, top-contact n-channel organic transistors are investigated using the gated four-probe (GFP) technique. The TFTs employ the small-molecule semiconductor N,N'-bis-(1H,1H-heptafluorobutyl)-1,7-dicyano-perylene-3,4:9,10-tetracarboxylic diimide (PDI-FCN2) and are fabricated on flexible plastic substrates. The transistors are air-stable and can be operated at low voltages of about 3 V, owing to a thin hybrid gate dielectric composed of aluminum oxide and a self-assembled molecular monolayer. The GFP method enabled a detailed investigation of the influence of a multitude of factors, including the gate-source and drain-source voltages, the contact length, the temperature and the contact metal, on the contact resistance. The contact properties are found to be very sensitive to the thickness of the organic semiconductor layer. In transistors in which this layer is relatively thin, ohmic contact resistances as small as about 0.6 Ohm cm were measured. In transistors with a relatively thick organic semiconductor layer, device physics becomes more complex and the current-voltage characteristics of the contact become nonlinear. Space-charge limited currents are identified as the probable origin of this nonlinear behavior. The good performance of the PDI-FCN2 transistors allows the realization of simple integrated circuits. Flexible organic complementary ring oscillators are fabricated and signal propagation delays per stage as short as 6 µs are demonstrated at a supply voltage of 3.6 V.

Contact Effects in Organic Transistors

Frederik Sebastian Ante

Organic thin-film transistors (TFTs) are of interest for applications that require electronic functionality with low or medium complexity distributed over large areas on unconventional substrates, such as flexible polymeric films. Generally these are applications in which the use of silicon devices and circuits is technically or economically not feasible. Examples include flexible displays and large-area sensor arrays. The static and dynamic performance of state-of-the-art organic p-channel transistors is already sufficient for applications in which the transistors operate with frequencies of a few tens of kilohertz. Strategies to improve the performance of organic TFTs include improvements in the field-effect mobility of the charge carriers in the organic semiconductor layer and more aggressive scaling of the transistor dimensions. Additional advances are also required in the environmental and operational stability of organic TFTs and in the application of controlled contact doping for the reduction of the contact resistance of organic TFTs. In this thesis, high-resolution silicon stencil masks are introduced to pattern top-contact organic TFTs with lateral dimensions as small as 0.8 µm. Taking advantage of the recently synthesized high-mobility air-stable organic semiconductor dinaphtho[2,3-b:2'3'-f]thieno[3,2-b]thiophene (DNTT), polycrystalline organic p-channel TFTs with excellent air-stability and an intrinsic mobility of 3.4 cm2/Vs were fabricated. The transistors employ an ultra-thin gate dielectric based on a plasma-grown oxide layer in combination with an organic self-assembled monolayer (gate capacitance ∼1 µF/cm2), allowing the TFTs to operate with low voltages of about 3 V. Transistors with dimensions of less than 100 nm were manufactured using polymer resist shadow masks that have been fabricated by electron-beam lithography. Thanks to the 5 nm thick gate dielectric the TFTs show no short-channel effects. The subthreshold swing, the on/off current ratio, and the threshold voltage are comparable to long-channel TFTs with lateral dimensions of ∼100 µm. However, organic transistors with reduced dimensions are often limited by the energy barrier at the interface between the semiconductor and the source/drain contacts. One approach to reduce this energy barrier is the introduction of a strong electron acceptor into the contact area that acts as a dopant. With contact doping, the contact resistance is reduced and the effective mobility of short-channel TFTs increases by more than 200%. Transistors (without doping) with lateral dimensions of ∼1 µm have a transconductance of about 1 S/m, so that the TFTs operate at frequencies of several megahertz. The influence of strongly reduced lateral dimensions on the contact resistance and the maximum operation frequency is investigated and scaling limitations are discussed.

EPFL2011

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high-integration density, but also to replace thin-film transistors in large-area electronics. This thesis investigates the use of wet-chemically grown ZnO nanowires for the fabrication of high-performance, low-voltage field-effect transistors (FETs). The first part of this thesis addresses the electrical characteristics of the wet-chemically grown ZnO nanowires. The as-grown ZnO nanowires are highly conductive due to a large charge-carrier concentration caused by dopants unintentionally incorporated into the ZnO nanowires during the synthesis. This large charge-carrier concentration makes it difficult to modulate the conductivity of the nanowires by an external electric field, so that the as-grown wires are not suitable for FETs. A post-growth annealing step is employed to dramatically reduce the charge-carrier concentration of the nanowires which makes it possible to fabricate FETs with useful characteristics. ZnO-nanowire FETs in a global back-gate geometry based on annealed ZnO nanowires have a transconductance of 300 nS, an on/off current ratio of 107 and a subthrehold slope of 500 mV/decade. The maximum field-effect mobility of the annealed ZnO nanowires is around 50 cm2/Vs. An important requirement to obtain good FET characterisitcs is to minimize the influence of the source and drain contact resistance on the total device resistance. The material used for the source and drain contacts in this thesis is aluminum. It is demonstrated that the use of a plasma treatment in the contact regions prior to the evaporation of the aluminum contacts can greatly influence the contact properties between ZnO and aluminum. An argon-plasma treatment locally increases the charge-carrier concentration in the ZnO. It is shown that the doping effect of the argon-plasma treatment can be exploited to reduce the contact resistance between alumiunm and ZnO and improve the electrical performance of the FETs. In the second part of this thesis, the influence of the ambient air on the electrical characteristics of the ZnO-nanowire FETs is investigated. The electrical conductivity of the FETs is strongly affected by the distinct atmospheric conditions, which makes it difficult to obtain reliable FET characteristics. The potential of a self-assembled monolayer (SAM) based on fluoroalkylphosphonic acid molecules to passivate the ZnO nanowires against the undesirable effects of the ambient and to stabilize the electrical performance of ZnO-nanowire FETs is demonstrated. The stabilizing effect is attributed to the formation of a densely packed, hydrophobic SAM on the surface of ZnO and aluminum oxide. The quality of the hydrophobic SAMs is confirmed by means of water-contact-angle measurements on SAM-covered ZnO single crystals that show a contact angle of more than 110°. The third part of this thesis is dedicated to the fabrication of high-performance ZnO-nanowire FETs with patterned metal top-gate electrodes. A top-gate fabrication process is developed that uses a very thin gate dielectric consisting only of an alkylphosphonic acid SAM that can be deposited from solution. The insulating quality of the SAM is investigated for top-gate FETs that utilize either gold or aluminum for the top-gate electrode. Gold top-gate FETs show a transconductance of 1 µS, an on/off current ratio of 107, and a steep subthreshold slope of 90 mV/decade. The thin gate dielectric makes it possible to operate the gold top-gate FETs at low voltages of 1 V and simultaneously reduces the undesired gate current by more than three orders of magnitude compared to gold top-gate FETs that have been fabricated without a gate dielectric (MESFETs). The gate current of the gold top-gate FETs with SAM gate dielectric is as low as 1 pA for gate-source voltages between -1 V and 0.5 V. When aluminum is used for the top-gate electrode, a hybrid dielectric is formed at the interface between the SAM and the aluminum, consisting of the SAM and a spontaneously formed aluminum oxide layer. Owing to the hybrid gate dielectric, the aluminum top-gate FETs are operated with gate currents below 1 pA for voltages up to 3 V. The top-gate fabrication process does not require temperatures above 160 °C, which makes it possible to fabricate FETs on unconventional substrates that cannot tolerate high temperatures, such as glass or flexible plastics. Integrated circuits on single ZnO nanowires that are fabricated on glass and plastic substrates are demonstrated. The maximum switching frequency of the inverters is 1 MHz.

EPFL2011

The Effect of Interface Modification on the Properties of Organic Thin-Film Transistors

Franziska Dora Fleischli

In organic thin-film transistors (OTFTs), the conducting channel is located near the interface between the organic semiconductor and the dielectric; this interface is crucial for transistor performance. The goal of this thesis is to study the effect of this interface, especially when it is modified either by surface treatments or self-assembled monolayers. For this purpose, OTFTs based on pentacene and doped silicon wafer gate electrode and gold top contacts are fabricated. The dielectric is either silicon oxide (SiO2) or polyimide (PI). The dielectric surface affects both the growth of the pentacene film on the top of it and the electric performance of the transistor. The pentacene film morphology is studied on treated and untreated SiO2 and PI surfaces by AFM and water contact angle measurements. Depending on the nature of the dielectric surface, traps or charge transfer centers are introduced which then affect the performance of the transistor. The transistor performance is determined by measuring the drain current as it is dependent upon the drain and gate voltage. The contributions of the channel and the contacts are separated by 4-probe measurements (at floating and non-floating gate). The transistors with untreated dielectrics are first characterized. The dependence on the channel length, the thickness and the morphology of the pentacene film is studied. The short channels (2 – 20 µm) are patterned by stencil masks; the long channels (100 – 600 µm) by steel masks. The results show that the transistors with a channel length of 20 µm and smaller are limited by the contacts, while the transistors with a channel length between 100 and 600 µm are dominated by the channel, and thus the traps and residual carriers in the channel. The pentacene film morphology has more influence on the contact resistance than on the channel behavior. To study the effect of the interface modifications, the transistor behavior should be dominated by the channel and the contact effects minimized; hence, long-channel transistors are used. The dielectric surfaces are treated by plasma or pH solutions prior to the pentacene deposition resulting in a variety of defects. The defects are distinguished by those which lead to a change in the film growth and those which affect the electric performance by introducing traps or charge transfer centers. To overcome the influence of the dielectric surface, the oxide dielectric is passivated by a self-assembled monolayer (SAM). The neutral SAM acts as a spacer between the dielectric and the pentacene film and thus enhances the transistor performance. The polar SAMs also introduce a dipole moment. A series of molecules with a similar length, but different end groups, are used to investigate the effect of the dipole moment. The main result of this study is that the nature and the quality of the gate and the contact interfaces are often more important for the performance of the transistors than the thin film morphology.

EPFL2010

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

EPFL2011

The Effect of Interface Modification on the Properties of Organic Thin-Film Transistors

Franziska Dora Fleischli

EPFL2010

Contact Effects in Organic Transistors

Frederik Sebastian Ante

EPFL2011