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K Users Caching Two Files: An Improved Achievable Rate

Publications associées (37)

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Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Temporal instruction fetch streaming

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...

2008

Miss Rate Prediction across Program Inputs and Cache Configurations

Chen Ding

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets and all cache configurations. This pape ...

2007

Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

ReCast: Boosting tag line buffer coverage in low-power high-level caches "for free"

Babak Falsafi

We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag set cache that filters a significant number of tag probes to the L2 tag array thus reducing power. The key contribution in ReCast is S-Shift, a simple indexin ...

2005

Miss Rate Prediction across All Program Inputs

Chen Ding

2003

Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Babak Falsafi

Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in t ...

2002

Reducing leakage in a high-performance deep-submicron instruction cache

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Making Pointer-Based Data Structures Cache Conscious

James Richard Larus

To narrow the widening gap between processor and memory performance, the authors propose improving the cache locality of pointer-manipulating programs and bolstering performance by careful placement of structure elements. It is concluded that considering p ...

IEEE2000