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A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Publications associées (34)

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High-temperature compatible 3D-integration processes for a vacuum-sealed CNT-based NEMS

Nico de Rooij, Danick Briand, Terunobu Akiyama, Rokhaya Gueye

A System-in-Package (SiP) concept for the 3D-integration of a Single Wall Carbon Nanotube (SWCNT) resonator with its CMOS driving electronics is presented. The key element of this advanced SiP is the monolithic 3D-integration of the MEMS with the CMOS elec ...

SPIE - International Society of Optical Engineering2013

Thermal Simulation of Liquid-Cooled Integrated Circuits

Arvind Raj Mahankali Sridhar

Growing demands for increased functionality in consumer electronics and for information technology-enabled services in various sectors have resulted in the rise of high-performance multiprocessor system-on-chips (MPSoCs) and three-dimensionally stacked int ...

EPFL2013

3.5-D Integration: A Case Study

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Vasileios Pavlidis, Shashi Kanth Bobba, Ciprian Seiculescu

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

3D-Integration of a Carbon Nanotube based RF-NEMS

Rokhaya Gueye

In the framework of the NanoTera project CabTuRes, a system-in-package for a nano-resonator was proposed, integrating CMOS driving electronics and vacuum encapsulation. This doctoral research aimed to investigate 3D-integration technologies for a Single-Wa ...

EPFL2013

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Carlotta Guiducci, Michail Zervas, Yusuf Leblebici, Yüksel Temiz

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012

Towards Multi-Fabric 3D Integration Architectures

Panagiotis Athanasopoulos

The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...

EPFL2012

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Luca Benini, Federico Angiolini, Subhasish Mitra

Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the f ...

2011

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3-Dimensional integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3-D multi-processor systems-onchip (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by mea ...

2011

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

Fengda Sun

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis ...

EPFL2011