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SABRes: Atomic Object Reads for In-Memory Rack-Scale Computing

Publications associées (32)

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Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Ties Jan Henderikus Kluter

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

Caching All Plans with Just One Optimizer Call

Anastasia Ailamaki, Ioannis Alagiannis, Debabrata Dash, Cristina Ileana Maier

Modern database management systems (DBMS) answer a multitude of complex queries on increasingly larger datasets. Given the complexities of the queries and the numerous design features, manual design is no longer an option. Instead, automatically designing ...

2010

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

Scheduling threads for constructive cache sharing on CMPs

Anastasia Ailamaki, Babak Falsafi

In chip multiprocessors (CMPs), limiting the number of offchip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in which concurrently scheduled threads share a largely overlappi ...

2007

Improving instruction cache performance in OLTP

Anastasia Ailamaki

Instruction-cache misses account for up to 40%; of execution time in online transaction processing (OLTP) database workloads. In contrast to data cache misses, instruction misses cannot be overlapped with out-of-order execution. Chip design limitations do ...

Association for Computing Machinery2006

Walking Four Machines By The Shore

Anastasia Ailamaki

Recent studies have shown that the hardware behavior of database workloads is suboptimal when compared to scientific workloads, and have identified the processor and memory subsystem as the true performance bottlenecks, when running decision-support worklo ...

2001

Two approaches for applet-based visible human slice extraction

Roger Hersch, Sebastian Gerlach

Real-time interactive slicing is a tool of choice for exploring 3D anatomic data sets such as the Visible Human. We offer real-time slicing on the Web by partitioning the application between a Java applet (the client) and the Web server. Two approaches for ...

SPIE-Int. Soc. Opt. Eng2001

Cache-Conscious Structure Definition

James Richard Larus

A program's cache performance can be improved by changing the organization and layout of its data---even complex, pointer-based data structures. Previous techniques improved the cache performance of these structures by arranging distinct instances to incre ...

ACM1999

Cache-Conscious Structure Layout

James Richard Larus

Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating program ...

ACM1999

Using Generational Garbage Collection to Implement Cache-Conscious Data Placement

James Richard Larus

The cost of accessing main memory is increasing. Machine designers have tried to mitigate the consequences of the processor and memory technology trends underlying this increasing gap with a variety of techniques to reduce or tolerate memory latency. These ...

ACM1998