A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services
Publications associées (37)
Graph Chatbot
Chattez avec Graph Search
Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.
AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.
Field programmable gate arrays (FPGA) are a recently developed family of programmable circuits. Like mask programmable gate arrays (MPGA), FPGAs implement thousands of logic gates. But, unlike MPGAs, a user can program an FPGA design as traditional program ...
Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...
In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambi ...
Recent studies show that emotion is a mechanism for fast decision-making in human and other animals. Mathematical models have been developed for describing emotion in mammals. These models, similar to other bio-inspired models, must be implemented in embed ...
Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...
This paper presents the implementation of the 1.2 mm2 HSDPA turbo decoder ASIC in 0.13 mum CMOS achieves a measured maximum frequency of 246 MHz, which translates to a maximum throughput of 20.2 Mb/s at 5.5 iterations. The peak throughput of 10.8 Mb/s requ ...
The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing perform ...