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The design of Wren, a Fast and Scalable Transactional Causally Consistent Geo-Replicated Key-Value Store

Publications associées (32)

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Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Seyed Armin Tajalli, Yusuf Leblebici

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional cl ...

Springer-Verlag2011

Clock Distribution Networks in 3-D Integrated Systems

Vasileios Pavlidis

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock di ...

2011

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010

Robust Synchronization of Absolute and Difference Clocks over Networks

Satish Babu Korada

We present a detailed re-examination of the problem of inexpensive yet accurate clock synchronization for networked devices. Based on an empirically validated, parsimonious abstraction of the CPU oscillator as a timing source, accessible via the TSC regist ...

2009

Clock and Power Distribution Networks for 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis

Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal ...

2009

Clock-Offset Tracking Software Algorithms For IR-UWB Energy-Detection Receivers

Jean-Yves Le Boudec, Ruben Merz, Manuel Flury

We present a clock-offset tracking algorithm for impulse-radio ultra-wide band (IR-UWB) energy-detection receivers. There is a complexity versus performance trade-off for the design of IR-UWB energy-detection receivers: Extremely low-complexity energy-dete ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Multiview Face Detection

Sébastien Marcel, Yann Rodriguez, Tiffany Sauquet

In this document, we address the problem of multiview face detection. This work extends the frontal face detection system developed at the IDIAP Research Institute to multiview face detection. The main state-of-the art techniques are reviewed and a novel a ...

IDIAP2005

Dynamically Trading Frequency for Complexity in a GALS Microprocessor

Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by “downsizing” hardware resources that are u ...

2004