Publications associées à Unified prefetching into instruction cache and branch target buffer

Determining an optimum quantity of interleaved instruction streams of defined coroutines

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include performing a first database operation by at least executing a first instruction stream associated with the first database operation. The first database opera ...

2023

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Hamish Mcniece Hill Nicholson, Periklis Chrysogelos

Accessing input data is a critical operation in data analytics: i) slow data access significantly degrades performance, and ii) storing everything in the fastest medium, i.e., memory, incurs high operational and hardware costs. Further, while GPUs offer in ...

2023

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Vishal Gupta

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Pierre Dillenbourg, Elmira Yadollahi, Ana Paiva

Spatial understanding and communication are essential skills in human interaction. An adequate understanding of others' spatial perspectives can increase the quality of the interaction, both perceptually and cognitively. In this paper, we take the first st ...

New York2022

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

HPCache: Memory-Efficient OLAP Through Proportional Caching

Anastasia Ailamaki, Hamish Mcniece Hill Nicholson, Periklis Chrysogelos

Analytical engines rely on in-memory caching to avoid disk accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- & time-based caching decisions, however, are a proxy of the expected query execution ...

ACM2022

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

2022

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Irem Boybat Kara, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Abu Sebastian

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

2022

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

2022

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Unified prefetching into instruction cache and branch target buffer

Determining an optimum quantity of interleaved instruction streams of defined coroutines

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

HPCache: Memory-Efficient OLAP Through Proportional Caching

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Columnar Storage Optimization and Caching for Data Lakes

Graph Chatbot

Chattez avec Graph Search

HetCache: Synergising NVMe Storage and GPU acceleration for Memory-Efficient Analytics

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

HPCache: Memory-Efficient OLAP Through Proportional Caching

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Columnar Storage Optimization and Caching for Data Lakes

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning