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An Analytical Model of Hardware Transactional Memory

Publications associées (33)

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Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska, Junaid Jameel Ahmad

The exploration of different design configurations of dynamic dataflow programs executed on many-core or multi-core platforms is, in general, a very difficult task. Determining a close-to-optimal partitioning, scheduling and buffer dimensioning configurati ...

2017

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Hasene Gülperi Özsema

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

EPFL2017

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We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

Towards Scalable Synchronization on Multi-Cores

Vasileios Trigonakis

The shift of commodity hardware from single- to multi-core processors in the early 2000s compelled software developers to take advantage of the available parallelism of multi-cores. Unfortunately, only few---so-called embarrassingly parallel---applications ...

EPFL2016

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Christos Kozyrakis

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devi ...

Ieee2016

Hierarchical Cycle Accounting: A New Method for Application Performance Tuning

Willy Zwaenepoel, Andrzej Pawel Nowak

To address the growing difficulty of performance debugging on modern processors with increasingly complex micro-architectures, we present Hierarchical Cycle Accounting (HCA), a structured, hierarchical, architecture-agnostic methodology for the identificat ...

2015

Accelerators for Data Processing

Yusuf Onur Koçberber

The explosive growth in digital data and its growing role in real-time analytics motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance and ush ...

EPFL2015

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Delegation is a thread synchronization technique where access to shared data is performed through a dedicated server thread. When a client thread requires shared data access, it makes a request to a server and waits for a response. This paper studies deleg ...

2015

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Giovanni De Micheli, Siang-Yun Lee

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

2014