Publications associées à Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Roman Hermida Correa

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constrain ...

2007

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Eric Vittoz, Yusuf Leblebici, Zeynep Toprak Deniz

This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing ...

2007

A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control

Giovanni De Micheli, Srinivasan Murali

When designing a System-on-Chip (SoC) using a Network-on- Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the Network Interfaces (NIs) needed to ...

2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

A Fast HW/SW FPGABased Thermal Emulation Framework for MultiProcessor SystemonChip

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are complex to design as they must execute multiple complex ...

2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

A Robust Self-calibrating Transmission Scheme for On-Chip Networks

Giovanni De Micheli, Paolo Ienne, Patrick Thiran, Frédéric Worm

Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are i ...

2005

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

Log-based architectures for general-purpose monitoring of deployed code

A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control

Reliability Support for On-chip Memories Using Networks-on-Chips

A Fast HW/SW FPGABased Thermal Emulation Framework for MultiProcessor SystemonChip

Applications of Specification and Design Languages for SoCs Selected papers from FDL'05

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

A Robust Self-calibrating Transmission Scheme for On-Chip Networks

Graph Chatbot

Chattez avec Graph Search

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

A Robust Self-calibrating Transmission Scheme for On-Chip Networks

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Applications of Specification and Design Languages for SoCs Selected papers from FDL'05

A Fast HW/SW FPGABased Thermal Emulation Framework for MultiProcessor SystemonChip

Reliability Support for On-chip Memories Using Networks-on-Chips

A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control

Log-based architectures for general-purpose monitoring of deployed code