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Circuit Design, Architecture and CAD for RRAM-based FPGAs

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Circuit Design, Architecture and CAD for RRAM-based FPGAs

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Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

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FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Plug-and-play TOF-PET Module Readout Based on TDC-on-FPGA and Gigabit Optical Fiber Network

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Live Demonstration: Quasi-Digital Portable Pen to Monitor Anaesthetics Delivery

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

Finding a Needle in the Haystack of Hardened Interconnect Patterns

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM