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Clock Jitter Compensation in High-Rate ADC Circuits

Publications associées (36)

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27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

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To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and theref ...

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Random sampling of bandlimited signals on graphs

Pierre Vandergheynst, Rémi Gribonval, Gilles Puy, Nicolas Tremblay

We study the problem of sampling

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Sampling information using timing is an approach that has received renewed attention in sampling theory. The question is how to map amplitude information into the timing domain. One such encoder, called time encoding machine, was introduced by Lazar and To ...

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An Algorithm to Compensate the Effects of Spurious PLL Tones in Spectrum Sensing Architectures

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In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used as a sampling clock to an analog-to-digital converter (ADC), it creates spurious sidebands in the sampled data a ...

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The issue of how to efficiently represent the data collected by a network of microphones recording spatio-temporal acoustic wave fields is addressed. Each sensor node in the network samples the sound field, quantizes the samples and transmits the encoded s ...

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Clock jitter estimation in noise

Ali H. Sayed

Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acqu ...

IEEE2011

Sampling Trajectories for Mobile Sensing

Martin Vetterli, Jayakrishnan Unnikrishnan

Classical sampling theory for sampling and reconstructing bandlimited fields in

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addresses the problem of sampling on lattice points. We consider a generalization of this problem, in which one samples the field along

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2011

Reducing spurious PLL tones in spectrum sensing architectures

Ali H. Sayed

In a non-ideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used in an analog-to-digital converter (ADC), it creates spurious tones in the sampled data as well. In spectrum sen ...

IEEE2011

Digital Suppression of Spurious PLL Tones in A/D Converters

Ali H. Sayed

In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used in an analog-to-digital converter (ADC), it injects the spurious tones into the sampled data. These distortions ...

IEEE2011

Sampling clock jitter estimation and compensation in ADC circuits

Ali H. Sayed

Clock timing jitters refer to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acqu ...

IEEE2010

Random sampling of bandlimited signals on graphs

Pierre Vandergheynst, Rémi Gribonval, Gilles Puy, Nicolas Tremblay

We study the problem of sampling

k

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Sampling Trajectories for Mobile Sensing

Martin Vetterli, Jayakrishnan Unnikrishnan

Classical sampling theory for sampling and reconstructing bandlimited fields in

\Re^d

addresses the problem of sampling on lattice points. We consider a generalization of this problem, in which one samples the field along

1

-dimensional spatial trajecto ...

2011