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In the framework of the NanoTera project CabTuRes, a system-in-package for a nano-resonator was proposed, integrating CMOS driving electronics and vacuum encapsulation. This doctoral research aimed to investigate 3D-integration technologies for a Single-Wa ...
Resonators for time and frequency reference applications are essential elements found in most electronic devices surrounding us. The continuous minimization and ubiquitous distribution of such electronic devices and circuits demands for resonators of small ...
This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is t ...
The main aim of this thesis is to examine the advantages of 3D stacking applied to microprocessors and related integrated microprocessor systems in the architectural level. In the succession of years microprocessors are aiming towards lower power consumpti ...
The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...
The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis ...
This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...
Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to ali ...
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In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...
3-Dimensional integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3-D multi-processor systems-onchip (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by mea ...
