Seyed Armin Tajalli, Yusuf Leblebici, Kiarash Gharibdoust
This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the referenc ...
Ieee2016