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Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning

Publications associées (205)

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Verification of STM on relaxed memory models

Rachid Guerraoui, Vasu Singh

Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed ...

Springer Verlag2011

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Rachid Guerraoui, Vincent Gramoli, Aleksandar Dragojevic, Pascal Felber

Software Transactional Memory (STM) promises to simplify concurrent programming without requiring specific hardware support. Yet, STM’s credibility lies on the extent to which it enables to leverage multicores and outperform sequential code. A recent CACM ...

2011

The VELOX Transactional Memory Stack

Rachid Guerraoui, Vincent Gramoli, Michal Kapalka, Aleksandar Dragojevic, Pascal Felber

The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer’s coordination methodology is cons ...

Institute of Electrical and Electronics Engineers2010

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Ties Jan Henderikus Kluter

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

Theory of Transactional Memory

Michal Kapalka

Transactional memory (TM) is a promising paradigm for concurrent programming, in which threads of an application communicate, and synchronize their actions, via inmemory transactions. Each transaction can perform any number of operations on shared data, an ...

EPFL2010

Exploring Programming Model-driven QoS Support for NoC-based Platforms

Giovanni De Micheli, Luca Benini, Federico Angiolini, Jaime Joven Murillo

Networks-on-Chip (NoCs) are being increasingly considered as a central enabling technology to communication-centric designs as more and more IP blocks are integrated on the same SoC. Embedded applications, in turn, are becoming extremely sophisticated, and ...

2010

Data-Oriented Transaction Execution

Anastasia Ailamaki, Frederick Ryan Johnson, Ippokratis Pandis

While hardware technology has undergone major advancements over the past decade, transaction processing systems have remained largely unchanged. The number of cores on a chip grows exponentially, following Moore's Law, allowing for an ever-increasing numbe ...

2010

Batch processing for efficient base-band operations in real-time GNSS software receivers

Pierre-André Farine, Cyril Botteron, Marcel Baracchi Frei

Personal Digital Assistants (PDAs) or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Navigation Satellite System (GNSS) functionalities. The new generation of portable ...

Inst Navigation, 815 15Th Th St Nw, Ste 832, Washington, Dc 20005 Usa2010

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Rachid Guerraoui, Maysam Yabandeh

Amodernmanycore architecture can be viewed as a distributed system with explicit message passing to communicate between cores. Ensuring the consistency of shared state replicated over several cores is the key to the well functioning of such a system. Yet, ...

2010

From high-level component-based models to distributed implementations

Joseph Sifakis

Although distributed systems are widely used nowadays, their implementation and deployment is still a time-consuming, error-prone, and hardly predictive task. In this paper, we propose a methodology for producing automatically efficient and correct-by-cons ...

ACM2010