An integrator-differentiator TIA using a multi-element pseudo-resistor in its DC servo loop for enhanced noise performance
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A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a n ...
A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current lev ...
Institute of Electrical and Electronics Engineers2013
A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current lev ...
Integrated Hall devices have the great advantage, over other magnetic sensors, that they can be fully fabricated by a standard CMOS process. However they are known to have a relatively large offset (i.e. residual voltage at zero magnetic field). Techniques ...
Minimally invasive monitoring of the electrical activity of specific cortical areas using implantable microsystems offers the promise of diagnosing neurological diseases, as well as detecting and identifying neural activity patterns which are specific to a ...
Techniques based on spin resonance effects are amongst the most powerful analytical methods in both modern chemistry and medicine. Recent years have seen a trend toward scaled-down detection coils, exploiting the fact that a reduction of the detector size ...
The development of front-end systems for the ATLAS tracker at the sLHC is now in progress and the availability of radiation tolerant buck converter ASICs enables the implementation of DC to DC converter based powering schemes. The front-end systems powered ...
In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV ...
Springer, 233 Spring Street, New York, Ny 10013, United States2009
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...